1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022 StarFive Technology Co., Ltd.
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: StarFive JH7110 DWMAC glue layer
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7110-dwmac
27 - starfive,jh7110-dwmac
28 - const: snps,dwmac-5.20
35 - description: GMAC main clock
36 - description: GMAC AHB clock
37 - description: PTP clock
38 - description: TX clock
39 - description: GTX clock
59 - description: MAC Reset signal.
60 - description: AHB Reset signal.
67 starfive,tx-use-rgmii-clk:
69 Tx clock is provided by external rgmii clock.
73 $ref: /schemas/types.yaml#/definitions/phandle-array
76 - description: phandle to syscon that configures phy mode
77 - description: Offset of phy mode selection
78 - description: Shift of phy mode selection
80 A phandle to syscon with two arguments that configure phy mode.
81 The argument one is the offset of phy mode selection, the
82 argument two is the shift of phy mode selection.
95 - $ref: snps,dwmac.yaml#
97 unevaluatedProperties: false
102 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
103 reg = <0x16030000 0x10000>;
104 clocks = <&clk 3>, <&clk 2>, <&clk 109>,
105 <&clk 6>, <&clk 111>;
106 clock-names = "stmmaceth", "pclk", "ptp_ref",
108 resets = <&rst 1>, <&rst 2>;
109 reset-names = "stmmaceth", "ahb";
110 interrupts = <7>, <6>, <5>;
111 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
112 phy-mode = "rgmii-id";
113 snps,multicast-filter-bins = <64>;
114 snps,perfect-filter-entries = <8>;
115 rx-fifo-depth = <2048>;
116 tx-fifo-depth = <2048>;
120 snps,force_thresh_dma_mode;
121 snps,axi-config = <&stmmac_axi_setup>;
122 snps,en-tx-lpi-clockgating;
125 starfive,syscon = <&aon_syscon 0xc 0x12>;
126 phy-handle = <&phy0>;
129 #address-cells = <1>;
131 compatible = "snps,dwmac-mdio";
133 phy0: ethernet-phy@0 {
138 stmmac_axi_setup: stmmac-axi-config {
140 snps,wr_osr_lmt = <4>;
141 snps,rd_osr_lmt = <4>;
142 snps,blen = <256 128 64 32 0 0 0>;