1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/renesas,etheravb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet AVB
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
21 - renesas,etheravb-r8a77470 # RZ/G1C
22 - renesas,etheravb-r8a7790 # R-Car H2
23 - renesas,etheravb-r8a7791 # R-Car M2-W
24 - renesas,etheravb-r8a7792 # R-Car V2H
25 - renesas,etheravb-r8a7793 # R-Car M2-N
26 - renesas,etheravb-r8a7794 # R-Car E2
27 - const: renesas,etheravb-rcar-gen2 # R-Car Gen2 and RZ/G1
31 - renesas,etheravb-r8a774a1 # RZ/G2M
32 - renesas,etheravb-r8a774b1 # RZ/G2N
33 - renesas,etheravb-r8a774c0 # RZ/G2E
34 - renesas,etheravb-r8a774e1 # RZ/G2H
35 - renesas,etheravb-r8a7795 # R-Car H3
36 - renesas,etheravb-r8a7796 # R-Car M3-W
37 - renesas,etheravb-r8a77961 # R-Car M3-W+
38 - renesas,etheravb-r8a77965 # R-Car M3-N
39 - renesas,etheravb-r8a77970 # R-Car V3M
40 - renesas,etheravb-r8a77980 # R-Car V3H
41 - renesas,etheravb-r8a77990 # R-Car E3
42 - renesas,etheravb-r8a77995 # R-Car D3
43 - renesas,etheravb-r8a779a0 # R-Car V3U
44 - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
48 - renesas,etheravb-r9a09g011 # RZ/V2M
49 - const: renesas,etheravb-rzv2m # RZ/V2M compatible
53 - renesas,r9a07g043-gbeth # RZ/G2UL
54 - renesas,r9a07g044-gbeth # RZ/G2{L,LC}
55 - renesas,r9a07g054-gbeth # RZ/V2L
56 - const: renesas,rzg2l-gbeth # RZ/{G2L,G2UL,V2L} family
82 description: Number of address cells for the MDIO bus.
86 description: Number of size cells on the MDIO bus.
89 renesas,no-ether-link:
92 Specify when a board does not provide a proper AVB_LINK signal.
94 renesas,ether-link-active-low:
97 Specify when the AVB_LINK signal is active-low instead of normal
100 rx-internal-delay-ps:
103 tx-internal-delay-ps:
107 "^ethernet-phy@[0-9a-f]$":
109 $ref: ethernet-phy.yaml#
124 - $ref: ethernet-controller.yaml#
131 - renesas,etheravb-rcar-gen2
132 - renesas,etheravb-r8a7795
133 - renesas,etheravb-r8a7796
134 - renesas,etheravb-r8a77961
135 - renesas,etheravb-r8a77965
140 - description: MAC register block
141 - description: Stream buffer
146 - description: MAC register block
153 - renesas,etheravb-rcar-gen2
154 - renesas,rzg2l-gbeth
166 rx-internal-delay-ps: false
172 const: renesas,etheravb-rzv2m
180 pattern: '^(ch(1?)[0-9])|ch20|ch21|dia|dib|err_a|err_b|mgmt_a|mgmt_b|line3$'
181 rx-internal-delay-ps: false
191 pattern: '^ch[0-9]+$'
194 - rx-internal-delay-ps
201 - renesas,etheravb-r8a774a1
202 - renesas,etheravb-r8a774b1
203 - renesas,etheravb-r8a774e1
204 - renesas,etheravb-r8a7795
205 - renesas,etheravb-r8a7796
206 - renesas,etheravb-r8a77961
207 - renesas,etheravb-r8a77965
208 - renesas,etheravb-r8a77970
209 - renesas,etheravb-r8a77980
210 - renesas,etheravb-r8a779a0
213 - tx-internal-delay-ps
216 tx-internal-delay-ps: false
222 const: renesas,etheravb-r8a77995
225 rx-internal-delay-ps:
232 const: renesas,etheravb-r8a77980
235 tx-internal-delay-ps:
242 const: renesas,rzg2l-gbeth
247 - description: Main clock
248 - description: Register access clock
249 - description: Reference clock for RGMII
260 const: renesas,etheravb-rzv2m
265 - description: Main clock
266 - description: Coherent Hub Interface clock
267 - description: gPTP reference clock
278 - description: AVB functional clock
279 - description: Optional TXC reference clock
286 additionalProperties: false
290 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
291 #include <dt-bindings/interrupt-controller/arm-gic.h>
292 #include <dt-bindings/power/r8a7795-sysc.h>
293 #include <dt-bindings/gpio/gpio.h>
298 avb: ethernet@e6800000 {
299 compatible = "renesas,etheravb-r8a7795",
300 "renesas,etheravb-rcar-gen3";
301 reg = <0xe6800000 0x800>, <0xe6a00000 0x10000>;
302 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
327 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6",
328 "ch7", "ch8", "ch9", "ch10", "ch11", "ch12",
329 "ch13", "ch14", "ch15", "ch16", "ch17", "ch18",
330 "ch19", "ch20", "ch21", "ch22", "ch23", "ch24";
331 clocks = <&cpg CPG_MOD 812>;
333 iommus = <&ipmmu_ds0 16>;
334 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
337 phy-handle = <&phy0>;
338 rx-internal-delay-ps = <0>;
339 tx-internal-delay-ps = <2000>;
340 #address-cells = <1>;
343 phy0: ethernet-phy@0 {
344 compatible = "ethernet-phy-id0022.1622",
345 "ethernet-phy-ieee802.3-c22";
346 rxc-skew-ps = <1500>;
348 interrupt-parent = <&gpio2>;
349 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
350 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;