1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/net/qcom,ethqos.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Ethernet ETHQOS device
10 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
13 dwmmac based Qualcomm ethernet devices which support Gigabit
14 ethernet (version v2.3.0 and onwards).
17 - $ref: snps,dwmac.yaml#
24 - qcom,sc8280xp-ethqos
38 - description: Combined signal for various interrupt events
39 - description: The interrupt that occurs when Rx exits the LPI state
73 unevaluatedProperties: false
77 #include <dt-bindings/interrupt-controller/arm-gic.h>
78 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
79 #include <dt-bindings/gpio/gpio.h>
81 ethernet: ethernet@7a80000 {
82 compatible = "qcom,qcs404-ethqos";
83 reg = <0x07a80000 0x10000>,
85 reg-names = "stmmaceth", "rgmii";
86 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
87 clocks = <&gcc GCC_ETH_AXI_CLK>,
88 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
89 <&gcc GCC_ETH_PTP_CLK>,
90 <&gcc GCC_ETH_RGMII_CLK>;
91 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
93 interrupt-names = "macirq", "eth_lpi";
95 rx-fifo-depth = <4096>;
96 tx-fifo-depth = <4096>;
99 snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
100 snps,reset-active-low;
101 snps,reset-delays-us = <0 10000 10000>;
103 pinctrl-names = "default";
104 pinctrl-0 = <ðernet_defaults>;
106 phy-handle = <&phy1>;
109 #address-cells = <0x1>;
112 compatible = "snps,dwmac-mdio";
114 compatible = "ethernet-phy-ieee802.3-c22";
115 device_type = "ethernet-phy";