1 # SPDX-License-Identifier: GPL-2.0+
4 $id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR803x PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
15 Bindings for Qualcomm Atheros AR803x PHYs
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
23 $ref: /schemas/types.yaml#/definitions/uint32
24 enum: [25000000, 50000000, 62500000, 125000000]
27 description: Clock output driver strength.
28 $ref: /schemas/types.yaml#/definitions/uint32
32 description: Disable Atheros SmartEEE feature.
37 If set, keep the PLL enabled even if there is no link. Useful if you
38 want to use the clock output without an ethernet link.
40 Only supported on the AR8031.
43 qca,smarteee-tw-us-100m:
44 description: EEE Tw parameter for 100M links.
45 $ref: /schemas/types.yaml#/definitions/uint32
49 qca,smarteee-tw-us-1g:
50 description: EEE Tw parameter for gigabit links.
51 $ref: /schemas/types.yaml#/definitions/uint32
57 RGMII I/O voltage regulator (see regulator/regulator.yaml).
59 The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
60 either connect this to the vddio-regulator (1.5V / 1.8V) or the
61 vddh-regulator (2.5V).
63 Only supported on the AR8031.
68 Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
69 $ref: /schemas/regulator/regulator.yaml
74 Dummy subnode to model the external connection of the PHY VDDH
76 $ref: /schemas/regulator/regulator.yaml
78 unevaluatedProperties: false
82 #include <dt-bindings/net/qca-ar803x.h>
88 phy-mode = "rgmii-id";
93 qca,clk-out-frequency = <125000000>;
94 qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
96 vddio-supply = <&vddio>;
98 vddio: vddio-regulator {
99 regulator-min-microvolt = <1800000>;
100 regulator-max-microvolt = <1800000>;
105 #include <dt-bindings/net/qca-ar803x.h>
108 #address-cells = <1>;
111 phy-mode = "rgmii-id";
116 qca,clk-out-frequency = <50000000>;
117 qca,keep-pll-enabled;
119 vddio-supply = <&vddh>;
121 vddh: vddh-regulator {