1 # SPDX-License-Identifier: GPL-2.0+
4 $id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
15 Bindings for NXP TJA11xx automotive PHYs
18 - $ref: ethernet-phy.yaml#
21 "^ethernet-phy@[0-9a-f]+$":
23 additionalProperties: false
25 Some packages have multiple PHYs. Secondary PHY should be defines as
26 subnode of the first (parent) PHY.
33 The ID number for the child PHY. Should be +1 of parent PHY.
38 The REF_CLK is provided for both transmitted and received data
39 in RMII mode. This clock signal is provided by the PHY and is
40 typically derived from an external 25MHz crystal. Alternatively,
41 a 50MHz clock signal generated by an external oscillator can be
42 connected to pin REF_CLK. A third option is to connect a 25MHz
43 clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
44 as input or output according to the actual circuit connection.
45 If present, indicates that the REF_CLK will be configured as
46 interface reference clock input when RMII mode enabled.
47 If not present, the REF_CLK will be configured as interface
48 reference clock output when RMII mode enabled.
49 Only supported on TJA1100 and TJA1101.
54 unevaluatedProperties: false
62 tja1101_phy0: ethernet-phy@4 {
72 tja1102_phy0: ethernet-phy@4 {
77 tja1102_phy1: ethernet-phy@5 {