1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Ethernet switch controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
16 QoS processing enabling delivery of differentiated services, and
17 security through TCAM-based frame processing using versatile content
18 aware processor (VCAP).
20 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
21 with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
22 IPv6 (S,G) multicast groups.
24 L3 security features include source guard and reverse path
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
26 IP tunnels (IP over GRE/IP).
28 The SparX-5 switch family targets managed Layer 2 and Layer 3
29 equipment in SMB, SME, and Enterprise where high port count
30 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
34 pattern: "^switch@[0-9a-f]+$"
37 const: microchip,sparx5-switch
41 - description: cpu target
42 - description: devices target
43 - description: general control block target
54 - description: register based extraction
55 - description: frame dma based extraction
56 - description: ptp interrupt
67 - description: Reset controller used for switch core reset (soft reset)
88 description: Switch port number
93 phandle of a Ethernet SerDes PHY. This defines which SerDes
94 instance will handle the Ethernet traffic.
98 This specifies the interface used by the Ethernet SerDes towards
102 description: Specifies bandwidth in Mbit/s allocated to the port.
103 $ref: "/schemas/types.yaml#/definitions/uint32"
108 phandle of a Ethernet PHY. This is optional and if provided it
109 points to the cuPHY used by the Ethernet SerDes.
113 phandle of an SFP. This is optional and used when not specifying
114 a cuPHY. It points to the SFP node that describes the SFP used by
121 Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
122 This is optional, and only needed if the default used index is
124 $ref: "/schemas/types.yaml#/definitions/uint32"
132 - microchip,bandwidth
151 additionalProperties: false
155 #include <dt-bindings/interrupt-controller/arm-gic.h>
156 switch: switch@600000000 {
157 compatible = "microchip,sparx5-switch";
159 <0x10004000 0x7fc000>,
160 <0x11010000 0xaf0000>;
161 reg-names = "cpu", "devices", "gcb";
162 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-names = "xtr";
165 reset-names = "switch";
167 #address-cells = <1>;
172 microchip,bandwidth = <1000>;
174 phy-handle = <&phy0>;
178 /* Then the 25G interfaces */
181 microchip,bandwidth = <25000>;
183 phy-mode = "10gbase-r";
185 managed = "in-band-status";
186 microchip,sd-sgpio = <365>;
190 microchip,bandwidth = <25000>;
192 phy-mode = "10gbase-r";
194 managed = "in-band-status";
195 microchip,sd-sgpio = <369>;
199 microchip,bandwidth = <25000>;
201 phy-mode = "10gbase-r";
203 managed = "in-band-status";
204 microchip,sd-sgpio = <373>;
208 microchip,bandwidth = <25000>;
210 phy-mode = "10gbase-r";
212 managed = "in-band-status";
213 microchip,sd-sgpio = <377>;
215 /* Finally the Management interface */
218 microchip,bandwidth = <1000>;
220 phy-handle = <&phy64>;
222 mac-address = [ 00 00 00 01 02 03 ];
228 # vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :