1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Ethernet switch controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
16 QoS processing enabling delivery of differentiated services, and
17 security through TCAM-based frame processing using versatile content
18 aware processor (VCAP).
20 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
21 with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
22 IPv6 (S,G) multicast groups.
24 L3 security features include source guard and reverse path
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
26 IP tunnels (IP over GRE/IP).
28 The SparX-5 switch family targets managed Layer 2 and Layer 3
29 equipment in SMB, SME, and Enterprise where high port count
30 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
34 pattern: "^switch@[0-9a-f]+$"
37 const: microchip,sparx5-switch
41 - description: cpu target
42 - description: devices target
43 - description: general control block target
54 - description: register based extraction
55 - description: frame dma based extraction
56 - description: ptp interrupt
67 - description: Reset controller used for switch core reset (soft reset)
77 additionalProperties: false
87 $ref: /schemas/net/ethernet-controller.yaml#
88 unevaluatedProperties: false
92 description: Switch port number
97 phandle of a Ethernet SerDes PHY. This defines which SerDes
98 instance will handle the Ethernet traffic.
101 description: Specifies bandwidth in Mbit/s allocated to the port.
102 $ref: /schemas/types.yaml#/definitions/uint32
107 Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
108 This is optional, and only needed if the default used index is
110 $ref: /schemas/types.yaml#/definitions/uint32
118 - microchip,bandwidth
135 additionalProperties: false
139 #include <dt-bindings/interrupt-controller/arm-gic.h>
140 switch: switch@600000000 {
141 compatible = "microchip,sparx5-switch";
143 <0x10004000 0x7fc000>,
144 <0x11010000 0xaf0000>;
145 reg-names = "cpu", "devices", "gcb";
146 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
147 interrupt-names = "xtr";
149 reset-names = "switch";
151 #address-cells = <1>;
156 microchip,bandwidth = <1000>;
158 phy-handle = <&phy0>;
162 /* Then the 25G interfaces */
165 microchip,bandwidth = <25000>;
167 phy-mode = "10gbase-r";
169 managed = "in-band-status";
170 microchip,sd-sgpio = <365>;
174 microchip,bandwidth = <25000>;
176 phy-mode = "10gbase-r";
178 managed = "in-band-status";
179 microchip,sd-sgpio = <369>;
183 microchip,bandwidth = <25000>;
185 phy-mode = "10gbase-r";
187 managed = "in-band-status";
188 microchip,sd-sgpio = <373>;
192 microchip,bandwidth = <25000>;
194 phy-mode = "10gbase-r";
196 managed = "in-band-status";
197 microchip,sd-sgpio = <377>;
199 /* Finally the Management interface */
202 microchip,bandwidth = <1000>;
204 phy-handle = <&phy64>;
206 mac-address = [ 00 00 00 01 02 03 ];
212 # vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :