1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Lan966x Ethernet switch controller
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
23 const: microchip,lan966x-switch
27 - description: cpu target
28 - description: general control block target
38 - description: register based extraction
39 - description: frame dma based extraction
40 - description: analyzer interrupt
41 - description: ptp interrupt
42 - description: ptp external interrupt
55 - description: Reset controller used for switch core reset (soft reset)
70 additionalProperties: false
76 $ref: /schemas/net/ethernet-controller.yaml#
77 unevaluatedProperties: false
91 Phandle of a Ethernet SerDes PHY
95 This specifies the interface used by the Ethernet SerDes towards
106 Phandle of a Ethernet PHY.
136 additionalProperties: false
140 #include <dt-bindings/interrupt-controller/arm-gic.h>
141 switch: switch@e0000000 {
142 compatible = "microchip,lan966x-switch";
143 reg = <0xe0000000 0x0100000>,
144 <0xe2000000 0x0800000>;
145 reg-names = "cpu", "gcb";
146 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
147 interrupt-names = "xtr";
148 resets = <&switch_reset 0>;
149 reset-names = "switch";
151 #address-cells = <1>;
156 phy-handle = <&phy0>;
157 phys = <&serdes 0 0>;
164 managed = "in-band-status";
165 phys = <&serdes 2 4>;