1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek STAR Ethernet MAC Controller
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
13 This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
39 additionalItems: false
46 $ref: /schemas/types.yaml#/definitions/phandle
48 Phandle to the device containing the PERICFG register range. This is used
49 to control the MII mode.
54 If present, indicates that the RMII reference clock, which is from external
55 PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.
60 If present, indicates that clock on RXC pad will be inversed.
65 If present, indicates that clock on TXC pad will be inversed.
69 unevaluatedProperties: false
80 unevaluatedProperties: false
84 #include <dt-bindings/interrupt-controller/arm-gic.h>
85 #include <dt-bindings/clock/mt8516-clk.h>
87 ethernet: ethernet@11180000 {
88 compatible = "mediatek,mt8516-eth";
89 reg = <0x11180000 0x1000>;
90 mediatek,pericfg = <&pericfg>;
91 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
92 clocks = <&topckgen CLK_TOP_RG_ETH>,
93 <&topckgen CLK_TOP_66M_ETH>,
94 <&topckgen CLK_TOP_133M_ETH>;
95 clock-names = "core", "reg", "trans";
96 phy-handle = <ð_phy>;
100 #address-cells = <1>;
103 eth_phy: ethernet-phy@0 {