1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Frame Engine Ethernet controller
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
14 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
50 $ref: /schemas/types.yaml#/definitions/phandle
52 Phandle to the syscon node that handles the port setup.
54 cci-control-port: true
57 $ref: /schemas/types.yaml#/definitions/phandle
59 Phandle to the mediatek hifsys controller used to provide various clocks
60 and reset to the system.
63 $ref: /schemas/types.yaml#/definitions/phandle-array
69 A list of phandle to the syscon node that handles the SGMII setup which is required for
70 those SoCs equipped with SGMII.
76 unevaluatedProperties: false
85 - $ref: "ethernet-controller.yaml#"
110 $ref: /schemas/types.yaml#/definitions/phandle
112 Phandle to the syscon node that handles the ports slew rate and
119 const: mediatek,mt7622-eth
136 - const: sgmii_tx250m
137 - const: sgmii_rx250m
138 - const: sgmii_cdr_ref
139 - const: sgmii_cdr_fb
148 $ref: /schemas/types.yaml#/definitions/phandle-array
154 List of phandles to wireless ethernet dispatch nodes.
156 mediatek,pcie-mirror:
157 $ref: /schemas/types.yaml#/definitions/phandle
159 Phandle to the mediatek pcie-mirror controller.
165 const: mediatek,mt7629-eth
184 - const: sgmii_tx250m
185 - const: sgmii_rx250m
186 - const: sgmii_cdr_ref
187 - const: sgmii_cdr_fb
188 - const: sgmii2_tx250m
189 - const: sgmii2_rx250m
190 - const: sgmii2_cdr_ref
191 - const: sgmii2_cdr_fb
196 $ref: /schemas/types.yaml#/definitions/phandle
198 Phandle to the syscon node that handles the path from GMAC to
209 const: mediatek,mt7986-eth
226 - const: sgmii_tx250m
227 - const: sgmii_rx250m
228 - const: sgmii_cdr_ref
229 - const: sgmii_cdr_fb
230 - const: sgmii2_tx250m
231 - const: sgmii2_rx250m
232 - const: sgmii2_cdr_ref
233 - const: sgmii2_cdr_fb
244 additionalProperties: false
246 - $ref: ethernet-controller.yaml#
251 const: mediatek,eth-mac
273 unevaluatedProperties: false
277 #include <dt-bindings/interrupt-controller/arm-gic.h>
278 #include <dt-bindings/interrupt-controller/irq.h>
279 #include <dt-bindings/clock/mt7622-clk.h>
280 #include <dt-bindings/power/mt7622-power.h>
283 #address-cells = <2>;
286 ethernet: ethernet@1b100000 {
287 compatible = "mediatek,mt7622-eth";
288 reg = <0 0x1b100000 0 0x20000>;
289 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
290 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
291 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
292 clocks = <&topckgen CLK_TOP_ETH_SEL>,
293 <ðsys CLK_ETH_ESW_EN>,
294 <ðsys CLK_ETH_GP0_EN>,
295 <ðsys CLK_ETH_GP1_EN>,
296 <ðsys CLK_ETH_GP2_EN>,
297 <&sgmiisys CLK_SGMII_TX250M_EN>,
298 <&sgmiisys CLK_SGMII_RX250M_EN>,
299 <&sgmiisys CLK_SGMII_CDR_REF>,
300 <&sgmiisys CLK_SGMII_CDR_FB>,
301 <&topckgen CLK_TOP_SGMIIPLL>,
302 <&apmixedsys CLK_APMIXED_ETH2PLL>;
303 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
304 "sgmii_tx250m", "sgmii_rx250m",
305 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
307 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
308 mediatek,ethsys = <ðsys>;
309 mediatek,sgmiisys = <&sgmiisys>;
310 cci-control-port = <&cci_control2>;
311 mediatek,pcie-mirror = <&pcie_mirror>;
312 mediatek,hifsys = <&hifsys>;
315 #address-cells = <1>;
319 #address-cells = <1>;
322 phy0: ethernet-phy@0 {
326 phy1: ethernet-phy@1 {
332 compatible = "mediatek,eth-mac";
334 phy-handle = <&phy0>;
339 compatible = "mediatek,eth-mac";
341 phy-handle = <&phy1>;
348 #include <dt-bindings/interrupt-controller/arm-gic.h>
349 #include <dt-bindings/interrupt-controller/irq.h>
350 #include <dt-bindings/clock/mt7622-clk.h>
353 #address-cells = <2>;
356 eth: ethernet@15100000 {
357 #define CLK_ETH_FE_EN 0
358 #define CLK_ETH_WOCPU1_EN 3
359 #define CLK_ETH_WOCPU0_EN 4
360 #define CLK_TOP_NETSYS_SEL 43
361 #define CLK_TOP_NETSYS_500M_SEL 44
362 #define CLK_TOP_NETSYS_2X_SEL 46
363 #define CLK_TOP_SGM_325M_SEL 47
364 #define CLK_APMIXED_NET2PLL 1
365 #define CLK_APMIXED_SGMPLL 3
367 compatible = "mediatek,mt7986-eth";
368 reg = <0 0x15100000 0 0x80000>;
369 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <ðsys CLK_ETH_FE_EN>,
374 <ðsys CLK_ETH_GP2_EN>,
375 <ðsys CLK_ETH_GP1_EN>,
376 <ðsys CLK_ETH_WOCPU1_EN>,
377 <ðsys CLK_ETH_WOCPU0_EN>,
378 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
379 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
380 <&sgmiisys0 CLK_SGMII_CDR_REF>,
381 <&sgmiisys0 CLK_SGMII_CDR_FB>,
382 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
383 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
384 <&sgmiisys1 CLK_SGMII_CDR_REF>,
385 <&sgmiisys1 CLK_SGMII_CDR_FB>,
386 <&topckgen CLK_TOP_NETSYS_SEL>,
387 <&topckgen CLK_TOP_NETSYS_SEL>;
388 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
389 "sgmii_tx250m", "sgmii_rx250m",
390 "sgmii_cdr_ref", "sgmii_cdr_fb",
391 "sgmii2_tx250m", "sgmii2_rx250m",
392 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
393 "netsys0", "netsys1";
394 mediatek,ethsys = <ðsys>;
395 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
396 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
397 <&topckgen CLK_TOP_SGM_325M_SEL>;
398 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
399 <&apmixedsys CLK_APMIXED_SGMPLL>;
401 #address-cells = <1>;
405 #address-cells = <1>;
408 phy5: ethernet-phy@0 {
409 compatible = "ethernet-phy-id67c9.de0a";
410 phy-mode = "2500base-x";
411 reset-gpios = <&pio 6 1>;
412 reset-deassert-us = <20000>;
416 phy6: ethernet-phy@1 {
417 compatible = "ethernet-phy-id67c9.de0a";
418 phy-mode = "2500base-x";
424 compatible = "mediatek,eth-mac";
425 phy-mode = "2500base-x";
426 phy-handle = <&phy5>;
431 compatible = "mediatek,eth-mac";
432 phy-mode = "2500base-x";
433 phy-handle = <&phy6>;