1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Frame Engine Ethernet controller
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
14 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
53 $ref: /schemas/types.yaml#/definitions/phandle
55 Phandle to the syscon node that handles the port setup.
57 cci-control-port: true
60 $ref: /schemas/types.yaml#/definitions/phandle
62 Phandle to the mediatek hifsys controller used to provide various clocks
63 and reset to the system.
66 $ref: /schemas/types.yaml#/definitions/phandle
68 Phandle to the syscon node that handles the path from GMAC to
72 $ref: /schemas/types.yaml#/definitions/phandle-array
78 A list of phandle to the syscon node that handles the SGMII setup which is required for
79 those SoCs equipped with SGMII.
82 $ref: /schemas/types.yaml#/definitions/phandle-array
88 List of phandles to wireless ethernet dispatch nodes.
91 $ref: /schemas/types.yaml#/definitions/phandle
93 Phandle to the mediatek wed-pcie controller.
99 unevaluatedProperties: false
108 - $ref: ethernet-controller.yaml#
114 - mediatek,mt2701-eth
115 - mediatek,mt7623-eth
132 mediatek,infracfg: false
135 $ref: /schemas/types.yaml#/definitions/phandle
137 Phandle to the syscon node that handles the ports slew rate and
142 mediatek,wed-pcie: false
149 - mediatek,mt7621-eth
164 mediatek,infracfg: false
168 mediatek,wed-pcie: false
174 const: mediatek,mt7622-eth
191 - const: sgmii_tx250m
192 - const: sgmii_rx250m
193 - const: sgmii_cdr_ref
194 - const: sgmii_cdr_fb
198 mediatek,infracfg: false
204 mediatek,pcie-mirror:
205 $ref: /schemas/types.yaml#/definitions/phandle
207 Phandle to the mediatek pcie-mirror controller.
209 mediatek,wed-pcie: false
215 const: mediatek,mt7629-eth
234 - const: sgmii_tx250m
235 - const: sgmii_rx250m
236 - const: sgmii_cdr_ref
237 - const: sgmii_cdr_fb
238 - const: sgmii2_tx250m
239 - const: sgmii2_rx250m
240 - const: sgmii2_cdr_ref
241 - const: sgmii2_cdr_fb
251 mediatek,wed-pcie: false
257 const: mediatek,mt7981-eth
274 - const: sgmii_tx250m
275 - const: sgmii_rx250m
276 - const: sgmii_cdr_ref
277 - const: sgmii_cdr_fb
278 - const: sgmii2_tx250m
279 - const: sgmii2_rx250m
280 - const: sgmii2_cdr_ref
281 - const: sgmii2_cdr_fb
285 mediatek,infracfg: false
295 const: mediatek,mt7986-eth
312 - const: sgmii_tx250m
313 - const: sgmii_rx250m
314 - const: sgmii_cdr_ref
315 - const: sgmii_cdr_fb
316 - const: sgmii2_tx250m
317 - const: sgmii2_rx250m
318 - const: sgmii2_cdr_ref
319 - const: sgmii2_cdr_fb
323 mediatek,infracfg: false
333 const: mediatek,mt7988-eth
350 - const: ethwarp_wocpu2
351 - const: ethwarp_wocpu1
352 - const: ethwarp_wocpu0
356 - const: sgmii_tx250m
357 - const: sgmii_rx250m
358 - const: sgmii2_tx250m
359 - const: sgmii2_rx250m
360 - const: top_usxgmii0_sel
361 - const: top_usxgmii1_sel
362 - const: top_sgm0_sel
363 - const: top_sgm1_sel
364 - const: top_xfi_phy0_xtal_sel
365 - const: top_xfi_phy1_xtal_sel
366 - const: top_eth_gmii_sel
367 - const: top_eth_refck_50m_sel
368 - const: top_eth_sys_200m_sel
369 - const: top_eth_sys_sel
370 - const: top_eth_xgmii_sel
371 - const: top_eth_mii_sel
372 - const: top_netsys_sel
373 - const: top_netsys_500m_sel
374 - const: top_netsys_pao_2x_sel
375 - const: top_netsys_sync_250m_sel
376 - const: top_netsys_ppefb_250m_sel
377 - const: top_netsys_warp_sel
391 unevaluatedProperties: false
393 - $ref: ethernet-controller.yaml#
398 const: mediatek,eth-mac
415 unevaluatedProperties: false
419 #include <dt-bindings/interrupt-controller/arm-gic.h>
420 #include <dt-bindings/interrupt-controller/irq.h>
421 #include <dt-bindings/clock/mt7622-clk.h>
422 #include <dt-bindings/power/mt7622-power.h>
425 #address-cells = <2>;
428 ethernet: ethernet@1b100000 {
429 compatible = "mediatek,mt7622-eth";
430 reg = <0 0x1b100000 0 0x20000>;
431 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
432 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
433 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
434 clocks = <&topckgen CLK_TOP_ETH_SEL>,
435 <ðsys CLK_ETH_ESW_EN>,
436 <ðsys CLK_ETH_GP0_EN>,
437 <ðsys CLK_ETH_GP1_EN>,
438 <ðsys CLK_ETH_GP2_EN>,
439 <&sgmiisys CLK_SGMII_TX250M_EN>,
440 <&sgmiisys CLK_SGMII_RX250M_EN>,
441 <&sgmiisys CLK_SGMII_CDR_REF>,
442 <&sgmiisys CLK_SGMII_CDR_FB>,
443 <&topckgen CLK_TOP_SGMIIPLL>,
444 <&apmixedsys CLK_APMIXED_ETH2PLL>;
445 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
446 "sgmii_tx250m", "sgmii_rx250m",
447 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
449 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
450 mediatek,ethsys = <ðsys>;
451 mediatek,sgmiisys = <&sgmiisys>;
452 cci-control-port = <&cci_control2>;
453 mediatek,pcie-mirror = <&pcie_mirror>;
454 mediatek,hifsys = <&hifsys>;
457 #address-cells = <1>;
461 #address-cells = <1>;
464 phy0: ethernet-phy@0 {
468 phy1: ethernet-phy@1 {
474 compatible = "mediatek,eth-mac";
476 phy-handle = <&phy0>;
481 compatible = "mediatek,eth-mac";
483 phy-handle = <&phy1>;
490 #include <dt-bindings/interrupt-controller/arm-gic.h>
491 #include <dt-bindings/interrupt-controller/irq.h>
492 #include <dt-bindings/clock/mt7622-clk.h>
495 #address-cells = <2>;
498 eth: ethernet@15100000 {
499 #define CLK_ETH_FE_EN 0
500 #define CLK_ETH_WOCPU1_EN 3
501 #define CLK_ETH_WOCPU0_EN 4
502 #define CLK_TOP_NETSYS_SEL 43
503 #define CLK_TOP_NETSYS_500M_SEL 44
504 #define CLK_TOP_NETSYS_2X_SEL 46
505 #define CLK_TOP_SGM_325M_SEL 47
506 #define CLK_APMIXED_NET2PLL 1
507 #define CLK_APMIXED_SGMPLL 3
509 compatible = "mediatek,mt7986-eth";
510 reg = <0 0x15100000 0 0x80000>;
511 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <ðsys CLK_ETH_FE_EN>,
516 <ðsys CLK_ETH_GP2_EN>,
517 <ðsys CLK_ETH_GP1_EN>,
518 <ðsys CLK_ETH_WOCPU1_EN>,
519 <ðsys CLK_ETH_WOCPU0_EN>,
520 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
521 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
522 <&sgmiisys0 CLK_SGMII_CDR_REF>,
523 <&sgmiisys0 CLK_SGMII_CDR_FB>,
524 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
525 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
526 <&sgmiisys1 CLK_SGMII_CDR_REF>,
527 <&sgmiisys1 CLK_SGMII_CDR_FB>,
528 <&topckgen CLK_TOP_NETSYS_SEL>,
529 <&topckgen CLK_TOP_NETSYS_SEL>;
530 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
531 "sgmii_tx250m", "sgmii_rx250m",
532 "sgmii_cdr_ref", "sgmii_cdr_fb",
533 "sgmii2_tx250m", "sgmii2_rx250m",
534 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
535 "netsys0", "netsys1";
536 mediatek,ethsys = <ðsys>;
537 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
538 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
539 <&topckgen CLK_TOP_SGM_325M_SEL>;
540 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
541 <&apmixedsys CLK_APMIXED_SGMPLL>;
543 #address-cells = <1>;
547 #address-cells = <1>;
550 phy5: ethernet-phy@0 {
551 compatible = "ethernet-phy-id67c9.de0a";
552 phy-mode = "2500base-x";
553 reset-gpios = <&pio 6 1>;
554 reset-deassert-us = <20000>;
558 phy6: ethernet-phy@1 {
559 compatible = "ethernet-phy-id67c9.de0a";
560 phy-mode = "2500base-x";
566 compatible = "mediatek,eth-mac";
567 phy-mode = "2500base-x";
568 phy-handle = <&phy5>;
573 compatible = "mediatek,eth-mac";
574 phy-mode = "2500base-x";
575 phy-handle = <&phy6>;