1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Frame Engine Ethernet controller
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
14 The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
50 $ref: /schemas/types.yaml#/definitions/phandle
52 Phandle to the syscon node that handles the port setup.
54 cci-control-port: true
57 $ref: /schemas/types.yaml#/definitions/phandle
59 Phandle to the mediatek hifsys controller used to provide various clocks
60 and reset to the system.
63 $ref: /schemas/types.yaml#/definitions/phandle-array
69 A list of phandle to the syscon node that handles the SGMII setup which is required for
70 those SoCs equipped with SGMII.
73 $ref: /schemas/types.yaml#/definitions/phandle-array
79 List of phandles to wireless ethernet dispatch nodes.
85 unevaluatedProperties: false
94 - $ref: "ethernet-controller.yaml#"
100 - mediatek,mt2701-eth
101 - mediatek,mt7623-eth
119 $ref: /schemas/types.yaml#/definitions/phandle
121 Phandle to the syscon node that handles the ports slew rate and
130 const: mediatek,mt7622-eth
147 - const: sgmii_tx250m
148 - const: sgmii_rx250m
149 - const: sgmii_cdr_ref
150 - const: sgmii_cdr_fb
158 mediatek,pcie-mirror:
159 $ref: /schemas/types.yaml#/definitions/phandle
161 Phandle to the mediatek pcie-mirror controller.
167 const: mediatek,mt7629-eth
186 - const: sgmii_tx250m
187 - const: sgmii_rx250m
188 - const: sgmii_cdr_ref
189 - const: sgmii_cdr_fb
190 - const: sgmii2_tx250m
191 - const: sgmii2_rx250m
192 - const: sgmii2_cdr_ref
193 - const: sgmii2_cdr_fb
198 $ref: /schemas/types.yaml#/definitions/phandle
200 Phandle to the syscon node that handles the path from GMAC to
213 const: mediatek,mt7986-eth
230 - const: sgmii_tx250m
231 - const: sgmii_rx250m
232 - const: sgmii_cdr_ref
233 - const: sgmii_cdr_fb
234 - const: sgmii2_tx250m
235 - const: sgmii2_rx250m
236 - const: sgmii2_cdr_ref
237 - const: sgmii2_cdr_fb
246 $ref: /schemas/types.yaml#/definitions/phandle
248 Phandle to the mediatek wed-pcie controller.
253 additionalProperties: false
255 - $ref: ethernet-controller.yaml#
260 const: mediatek,eth-mac
282 unevaluatedProperties: false
286 #include <dt-bindings/interrupt-controller/arm-gic.h>
287 #include <dt-bindings/interrupt-controller/irq.h>
288 #include <dt-bindings/clock/mt7622-clk.h>
289 #include <dt-bindings/power/mt7622-power.h>
292 #address-cells = <2>;
295 ethernet: ethernet@1b100000 {
296 compatible = "mediatek,mt7622-eth";
297 reg = <0 0x1b100000 0 0x20000>;
298 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
299 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
300 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
301 clocks = <&topckgen CLK_TOP_ETH_SEL>,
302 <ðsys CLK_ETH_ESW_EN>,
303 <ðsys CLK_ETH_GP0_EN>,
304 <ðsys CLK_ETH_GP1_EN>,
305 <ðsys CLK_ETH_GP2_EN>,
306 <&sgmiisys CLK_SGMII_TX250M_EN>,
307 <&sgmiisys CLK_SGMII_RX250M_EN>,
308 <&sgmiisys CLK_SGMII_CDR_REF>,
309 <&sgmiisys CLK_SGMII_CDR_FB>,
310 <&topckgen CLK_TOP_SGMIIPLL>,
311 <&apmixedsys CLK_APMIXED_ETH2PLL>;
312 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
313 "sgmii_tx250m", "sgmii_rx250m",
314 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
316 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
317 mediatek,ethsys = <ðsys>;
318 mediatek,sgmiisys = <&sgmiisys>;
319 cci-control-port = <&cci_control2>;
320 mediatek,pcie-mirror = <&pcie_mirror>;
321 mediatek,hifsys = <&hifsys>;
324 #address-cells = <1>;
328 #address-cells = <1>;
331 phy0: ethernet-phy@0 {
335 phy1: ethernet-phy@1 {
341 compatible = "mediatek,eth-mac";
343 phy-handle = <&phy0>;
348 compatible = "mediatek,eth-mac";
350 phy-handle = <&phy1>;
357 #include <dt-bindings/interrupt-controller/arm-gic.h>
358 #include <dt-bindings/interrupt-controller/irq.h>
359 #include <dt-bindings/clock/mt7622-clk.h>
362 #address-cells = <2>;
365 eth: ethernet@15100000 {
366 #define CLK_ETH_FE_EN 0
367 #define CLK_ETH_WOCPU1_EN 3
368 #define CLK_ETH_WOCPU0_EN 4
369 #define CLK_TOP_NETSYS_SEL 43
370 #define CLK_TOP_NETSYS_500M_SEL 44
371 #define CLK_TOP_NETSYS_2X_SEL 46
372 #define CLK_TOP_SGM_325M_SEL 47
373 #define CLK_APMIXED_NET2PLL 1
374 #define CLK_APMIXED_SGMPLL 3
376 compatible = "mediatek,mt7986-eth";
377 reg = <0 0x15100000 0 0x80000>;
378 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <ðsys CLK_ETH_FE_EN>,
383 <ðsys CLK_ETH_GP2_EN>,
384 <ðsys CLK_ETH_GP1_EN>,
385 <ðsys CLK_ETH_WOCPU1_EN>,
386 <ðsys CLK_ETH_WOCPU0_EN>,
387 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
388 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
389 <&sgmiisys0 CLK_SGMII_CDR_REF>,
390 <&sgmiisys0 CLK_SGMII_CDR_FB>,
391 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
392 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
393 <&sgmiisys1 CLK_SGMII_CDR_REF>,
394 <&sgmiisys1 CLK_SGMII_CDR_FB>,
395 <&topckgen CLK_TOP_NETSYS_SEL>,
396 <&topckgen CLK_TOP_NETSYS_SEL>;
397 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
398 "sgmii_tx250m", "sgmii_rx250m",
399 "sgmii_cdr_ref", "sgmii_cdr_fb",
400 "sgmii2_tx250m", "sgmii2_rx250m",
401 "sgmii2_cdr_ref", "sgmii2_cdr_fb",
402 "netsys0", "netsys1";
403 mediatek,ethsys = <ðsys>;
404 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
405 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
406 <&topckgen CLK_TOP_SGM_325M_SEL>;
407 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
408 <&apmixedsys CLK_APMIXED_SGMPLL>;
410 #address-cells = <1>;
414 #address-cells = <1>;
417 phy5: ethernet-phy@0 {
418 compatible = "ethernet-phy-id67c9.de0a";
419 phy-mode = "2500base-x";
420 reset-gpios = <&pio 6 1>;
421 reset-deassert-us = <20000>;
425 phy6: ethernet-phy@1 {
426 compatible = "ethernet-phy-id67c9.de0a";
427 phy-mode = "2500base-x";
433 compatible = "mediatek,eth-mac";
434 phy-mode = "2500base-x";
435 phy-handle = <&phy5>;
440 compatible = "mediatek,eth-mac";
441 phy-mode = "2500base-x";
442 phy-handle = <&phy6>;