1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. One or more GPIO
14 lines are used to control which child bus is connected.
17 - $ref: /schemas/net/mdio-mux.yaml#
25 List of GPIOs used to control the multiplexer, least significant bit first.
33 unevaluatedProperties: false
38 An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
39 pair of GPIO lines. Child busses 2 and 3 populated with 4
43 compatible = "mdio-mux-gpio";
44 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
45 mdio-parent-bus = <&smi1>;
56 marvell,reg-init = <3 0x10 0 0x5777>,
60 interrupt-parent = <&gpio>;
61 interrupts = <10 8>; /* Pin 10, active low */
65 marvell,reg-init = <3 0x10 0 0x5777>,
69 interrupt-parent = <&gpio>;
70 interrupts = <10 8>; /* Pin 10, active low */
74 marvell,reg-init = <3 0x10 0 0x5777>,
78 interrupt-parent = <&gpio>;
79 interrupts = <10 8>; /* Pin 10, active low */
83 marvell,reg-init = <3 0x10 0 0x5777>,
87 interrupt-parent = <&gpio>;
88 interrupts = <10 8>; /* Pin 10, active low */
99 marvell,reg-init = <3 0x10 0 0x5777>,
103 interrupt-parent = <&gpio>;
104 interrupts = <12 8>; /* Pin 12, active low */
108 marvell,reg-init = <3 0x10 0 0x5777>,
112 interrupt-parent = <&gpio>;
113 interrupts = <12 8>; /* Pin 12, active low */
117 marvell,reg-init = <3 0x10 0 0x5777>,
121 interrupt-parent = <&gpio>;
122 interrupts = <12 8>; /* Pin 12, active low */
126 marvell,reg-init = <3 0x10 0 0x5777>,
130 interrupt-parent = <&gpio>;
131 interrupts = <12 8>; /* Pin 12, active low */