1 =============================================================================
2 Freescale Frame Manager Device Bindings
8 - FMan dTSEC/XGEC/mEMAC Node
13 =============================================================================
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 etc.) the FMan node will have child nodes for each of them.
25 Value type: <stringlist>
26 Definition: Must include "fsl,fman"
27 FMan version can be determined via FM_IP_REV_1 register in the
28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
30 beginning of the FMan node).
35 Definition: Specifies the index of the FMan unit.
37 The cell-index value may be used by the SoC, to identify the
38 FMan unit in the SoC memory map. In the table below,
39 there's a description of the cell-index use in each SoC:
42 register[bit] FMan unit cell-index
43 ============================================================
46 - P2041, P3041, P4080 P5020, P5040:
47 register[bit] FMan unit cell-index
48 ============================================================
51 (Second FM available only in P4080 and P5040)
53 - B4860, T1040, T2080, T4240:
54 register[bit] FMan unit cell-index
55 ============================================================
56 DCFG_CCSR_DEVDISR2[24] 1 0
57 DCFG_CCSR_DEVDISR2[25] 2 1
58 (Second FM available only in T4240)
60 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
61 the specific SoC "Device Configuration/Pin Control" Memory
66 Value type: <prop-encoded-array>
67 Definition: A standard property. Specifies the offset of the
68 following configuration registers:
69 - BMI configuration registers.
70 - QMI configuration registers.
71 - DMA configuration registers.
72 - FPM configuration registers.
73 - FMan controller configuration registers.
77 Value type: <prop-encoded-array>
78 Definition: A standard property.
82 Value type: <prop-encoded-array>
83 Definition: phandle for the fman input clock.
87 Value type: <stringlist>
88 Definition: "fmanclk" for the fman input clock.
92 Value type: <prop-encoded-array>
93 Definition: A pair of IRQs are specified in this property.
94 The first element is associated with the event interrupts and
95 the second element is associated with the error interrupts.
97 - fsl,qman-channel-range
99 Value type: <prop-encoded-array>
100 Definition: Specifies the range of the available dedicated
101 channels in the FMan. The first cell specifies the beginning
102 of the range and the second cell specifies the number of
104 Further information available at:
105 "Work Queue (WQ) Channel Assignments in the QMan" section
106 in DPAA Reference Manual.
111 Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
113 - fsl,erratum-a050385
116 Definition: A boolean property. Indicates the presence of the
117 erratum A050385 which indicates that DMA transactions that are
118 split can result in a FMan lock.
120 =============================================================================
125 FMan Internal memory - shared between all the FMan modules.
126 It contains data structures that are common and written to or read by
128 FMan internal memory is split into the following parts:
129 Packet buffering (Tx/Rx FIFOs)
130 Frames internal context
136 Value type: <stringlist>
137 Definition: Must include "fsl,fman-muram"
141 Value type: <prop-encoded-array>
142 Definition: A standard property.
143 Specifies the multi-user memory offset and the size within
149 compatible = "fsl,fman-muram";
150 ranges = <0 0x000000 0x28000>;
153 =============================================================================
158 The Frame Manager (FMan) supports several types of hardware ports:
159 Ethernet receiver (RX)
160 Ethernet transmitter (TX)
161 Offline/Host command (O/H)
167 Value type: <stringlist>
168 Definition: A standard property.
169 Must include one of the following:
170 - "fsl,fman-v2-port-oh" for FManV2 OH ports
171 - "fsl,fman-v2-port-rx" for FManV2 RX ports
172 - "fsl,fman-v2-port-tx" for FManV2 TX ports
173 - "fsl,fman-v3-port-oh" for FManV3 OH ports
174 - "fsl,fman-v3-port-rx" for FManV3 RX ports
175 - "fsl,fman-v3-port-tx" for FManV3 TX ports
180 Definition: Specifies the hardware port id.
181 Each hardware port on the FMan has its own hardware PortID.
182 Super set of all hardware Port IDs available at FMan Reference
183 Manual under "FMan Hardware Ports in Freescale Devices" table.
185 Each hardware port is assigned a 4KB, port-specific page in
186 the FMan hardware port memory region (which is part of the
187 FMan memory map). The first 4 KB in the FMan hardware ports
188 memory region is used for what are called common registers.
189 The subsequent 63 4KB pages are allocated to the hardware
191 The page of a specific port is determined by the cell-index.
195 Value type: <prop-encoded-array>
196 Definition: There is one reg region describing the port
197 configuration registers.
202 Definition: The default port rate is 1G.
203 If this property exists, the port is s 10G port.
205 - fsl,fman-best-effort-port
208 Definition: Can be defined only if 10G-support is set.
209 This property marks a best-effort 10G port (10G port that
210 may not be capable of line rate).
216 compatible = "fsl,fman-v2-port-tx";
217 reg = <0xa8000 0x1000>;
222 compatible = "fsl,fman-v2-port-rx";
223 reg = <0x88000 0x1000>;
228 compatible = "fsl,fman-v2-port-oh";
229 reg = <0x81000 0x1000>;
232 =============================================================================
233 FMan dTSEC/XGEC/mEMAC Node
237 mEMAC/dTSEC/XGEC are the Ethernet network interfaces
243 Value type: <stringlist>
244 Definition: A standard property.
245 Must include one of the following:
246 - "fsl,fman-dtsec" for dTSEC MAC
247 - "fsl,fman-xgec" for XGEC MAC
248 - "fsl,fman-memac" for mEMAC MAC
253 Definition: Specifies the MAC id.
255 The cell-index value may be used by the FMan or the SoC, to
256 identify the MAC unit in the FMan (or SoC) memory map.
257 In the tables below there's a description of the cell-index
258 use, there are two tables, one describes the use of cell-index
259 by the FMan, the second describes the use by the SoC:
264 register[bit] MAC cell-index
265 ============================================================
267 FM_EPI[16+n] dTSECn n-1
268 FM_NPI[11+n] dTSECn n-1
272 register[bit] MAC cell-index
273 ============================================================
274 FM_EPI[16+n] mEMACn n-1
277 FM_NPI[11+n] mEMACn n-1
282 FM_EPI and FM_NPI are located in the FMan memory map.
286 - P2041, P3041, P4080 P5020, P5040:
287 register[bit] FMan MAC cell
289 ============================================================
290 DCFG_DEVDISR2[7] 1 XGEC 8
291 DCFG_DEVDISR2[7+n] 1 dTSECn n-1
292 DCFG_DEVDISR2[15] 2 XGEC 8
293 DCFG_DEVDISR2[15+n] 2 dTSECn n-1
296 - T1040, T2080, T4240, B4860:
297 register[bit] FMan MAC cell
299 ============================================================
300 DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1
301 DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1
304 EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
305 the specific SoC "Device Configuration/Pin Control" Memory
310 Value type: <prop-encoded-array>
311 Definition: A standard property.
315 Value type: <prop-encoded-array>
316 Definition: An array of two phandles - the first references is
317 the FMan RX port and the second is the TX port used by this
322 Value type: <phandle>
323 Definition: A phandle for 1EEE1588 timer.
326 Usage required for "fsl,fman-memac" MACs
327 Value type: <phandle>
328 Definition: A phandle for pcsphy.
331 Usage required for "fsl,fman-dtsec" MACs
332 Value type: <phandle>
333 Definition: A phandle for tbiphy.
337 fman1_tx28: port@a8000 {
339 compatible = "fsl,fman-v2-port-tx";
340 reg = <0xa8000 0x1000>;
343 fman1_rx8: port@88000 {
345 compatible = "fsl,fman-v2-port-rx";
346 reg = <0x88000 0x1000>;
349 ptp-timer: ptp_timer@fe000 {
350 compatible = "fsl,fman-ptp-timer";
351 reg = <0xfe000 0x1000>;
355 compatible = "fsl,fman-dtsec";
357 reg = <0xe0000 0x1000>;
358 fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
359 ptp-timer = <&ptp-timer>;
360 tbi-handle = <&tbi0>;
363 ============================================================================
366 Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
368 =============================================================================
373 The MDIO is a bus to which the PHY devices are connected.
379 Value type: <stringlist>
380 Definition: A standard property.
381 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
382 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
383 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
388 Value type: <prop-encoded-array>
389 Definition: A standard property.
393 Value type: <phandle>
394 Definition: A reference to the input clock of the controller
395 from which the MDC frequency is derived.
400 Definition: Specifies the external MDC frequency, in Hertz, to
401 be used. Requires that the input clock is specified in the
402 "clocks" property. See also: mdio.yaml.
406 Value type: <boolean>
407 Definition: Disable generation of preamble bits. See also:
411 Usage: required for external MDIO
412 Value type: <prop-encoded-array>
413 Definition: Event interrupt of external MDIO controller.
415 - fsl,fman-internal-mdio
416 Usage: required for internal MDIO
418 Definition: Fman has internal MDIO for internal PCS(Physical
419 Coding Sublayer) PHYs and external MDIO for external PHYs.
420 The settings and programming routines for internal/external
421 MDIO are different. Must be included for internal MDIO.
423 - fsl,erratum-a009885
425 Value type: <boolean>
426 Definition: Indicates the presence of the A009885
427 erratum describing that the contents of MDIO_DATA may
428 become corrupt unless it is read within 16 MDC cycles
429 of MDIO_CFG[BSY] being cleared, when performing an
432 - fsl,erratum-a011043
434 Value type: <boolean>
435 Definition: Indicates the presence of the A011043 erratum
436 describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
437 set when reading internal PCS registers. MDIO reads to
438 internal PCS registers may result in having the
439 MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
440 read data (MDIO_DATA[MDIO_DATA]) is correct.
441 Software may get false read error when reading internal
442 PCS registers through MDIO. As a workaround, all internal
443 MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
445 For internal PHY device on internal mdio bus, a PHY node should be created.
446 See the definition of the PHY node in booting-without-of.txt for an
447 example of how to define a PHY (Internal PHY has no interrupt line).
448 - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
449 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
450 PCS PHY addr must be '0'.
454 Example for FMan v2 external MDIO:
457 compatible = "fsl,fman-xmdio";
458 reg = <0xf1000 0x1000>;
459 interrupts = <101 2 0 0>;
462 Example for FMan v2 internal MDIO:
465 compatible = "fsl,fman-mdio";
466 reg = <0xe3120 0xee0>;
467 fsl,fman-internal-mdio;
471 device_type = "tbi-phy";
475 Example for FMan v3 internal MDIO:
478 compatible = "fsl,fman-memac-mdio";
479 reg = <0xf1000 0x1000>;
480 fsl,fman-internal-mdio;
482 pcsphy6: ethernet-phy@0 {
487 =============================================================================
491 #address-cells = <1>;
494 compatible = "fsl,fman"
495 ranges = <0 0x400000 0x100000>;
496 reg = <0x400000 0x100000>;
497 clocks = <&fman_clk>;
498 clock-names = "fmanclk";
502 fsl,qman-channel-range = <0x40 0xc>;
505 compatible = "fsl,fman-muram";
511 compatible = "fsl,fman-v2-port-oh";
512 reg = <0x81000 0x1000>;
517 compatible = "fsl,fman-v2-port-oh";
518 reg = <0x82000 0x1000>;
523 compatible = "fsl,fman-v2-port-oh";
524 reg = <0x83000 0x1000>;
529 compatible = "fsl,fman-v2-port-oh";
530 reg = <0x84000 0x1000>;
535 compatible = "fsl,fman-v2-port-oh";
536 reg = <0x85000 0x1000>;
541 compatible = "fsl,fman-v2-port-oh";
542 reg = <0x86000 0x1000>;
545 fman1_rx_0x8: port@88000 {
547 compatible = "fsl,fman-v2-port-rx";
548 reg = <0x88000 0x1000>;
551 fman1_rx_0x9: port@89000 {
553 compatible = "fsl,fman-v2-port-rx";
554 reg = <0x89000 0x1000>;
557 fman1_rx_0xa: port@8a000 {
559 compatible = "fsl,fman-v2-port-rx";
560 reg = <0x8a000 0x1000>;
563 fman1_rx_0xb: port@8b000 {
565 compatible = "fsl,fman-v2-port-rx";
566 reg = <0x8b000 0x1000>;
569 fman1_rx_0xc: port@8c000 {
571 compatible = "fsl,fman-v2-port-rx";
572 reg = <0x8c000 0x1000>;
575 fman1_rx_0x10: port@90000 {
577 compatible = "fsl,fman-v2-port-rx";
578 reg = <0x90000 0x1000>;
581 fman1_tx_0x28: port@a8000 {
583 compatible = "fsl,fman-v2-port-tx";
584 reg = <0xa8000 0x1000>;
587 fman1_tx_0x29: port@a9000 {
589 compatible = "fsl,fman-v2-port-tx";
590 reg = <0xa9000 0x1000>;
593 fman1_tx_0x2a: port@aa000 {
595 compatible = "fsl,fman-v2-port-tx";
596 reg = <0xaa000 0x1000>;
599 fman1_tx_0x2b: port@ab000 {
601 compatible = "fsl,fman-v2-port-tx";
602 reg = <0xab000 0x1000>;
605 fman1_tx_0x2c: port@ac0000 {
607 compatible = "fsl,fman-v2-port-tx";
608 reg = <0xac000 0x1000>;
611 fman1_tx_0x30: port@b0000 {
613 compatible = "fsl,fman-v2-port-tx";
614 reg = <0xb0000 0x1000>;
618 compatible = "fsl,fman-dtsec";
620 reg = <0xe0000 0x1000>;
621 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
622 tbi-handle = <&tbi5>;
626 compatible = "fsl,fman-dtsec";
628 reg = <0xe2000 0x1000>;
629 fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
630 tbi-handle = <&tbi6>;
634 compatible = "fsl,fman-dtsec";
636 reg = <0xe4000 0x1000>;
637 fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
638 tbi-handle = <&tbi7>;
642 compatible = "fsl,fman-dtsec";
644 reg = <0xe6000 0x1000>;
645 fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
646 tbi-handle = <&tbi8>;
650 compatible = "fsl,fman-dtsec";
652 reg = <0xf0000 0x1000>;
653 fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
654 tbi-handle = <&tbi9>;
658 compatible = "fsl,fman-xgec";
659 reg = <0xf0000 0x1000>;
660 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
664 compatible = "fsl,fman-ptp-timer";
665 reg = <0xfe000 0x1000>;
669 compatible = "fsl,fman-xmdio";
670 reg = <0xf1000 0x1000>;
671 interrupts = <101 2 0 0>;