1 =============================================================================
2 Freescale Frame Manager Device Bindings
8 - FMan dTSEC/XGEC/mEMAC Node
13 =============================================================================
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 etc.) the FMan node will have child nodes for each of them.
25 Value type: <stringlist>
26 Definition: Must include "fsl,fman"
27 FMan version can be determined via FM_IP_REV_1 register in the
28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
30 beginning of the FMan node).
35 Definition: Specifies the index of the FMan unit.
37 The cell-index value may be used by the SoC, to identify the
38 FMan unit in the SoC memory map. In the table below,
39 there's a description of the cell-index use in each SoC:
42 register[bit] FMan unit cell-index
43 ============================================================
46 - P2041, P3041, P4080 P5020, P5040:
47 register[bit] FMan unit cell-index
48 ============================================================
51 (Second FM available only in P4080 and P5040)
53 - B4860, T1040, T2080, T4240:
54 register[bit] FMan unit cell-index
55 ============================================================
56 DCFG_CCSR_DEVDISR2[24] 1 0
57 DCFG_CCSR_DEVDISR2[25] 2 1
58 (Second FM available only in T4240)
60 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
61 the specific SoC "Device Configuration/Pin Control" Memory
66 Value type: <prop-encoded-array>
67 Definition: A standard property. Specifies the offset of the
68 following configuration registers:
69 - BMI configuration registers.
70 - QMI configuration registers.
71 - DMA configuration registers.
72 - FPM configuration registers.
73 - FMan controller configuration registers.
77 Value type: <prop-encoded-array>
78 Definition: A standard property.
82 Value type: <prop-encoded-array>
83 Definition: phandle for the fman input clock.
87 Value type: <stringlist>
88 Definition: "fmanclk" for the fman input clock.
92 Value type: <prop-encoded-array>
93 Definition: A pair of IRQs are specified in this property.
94 The first element is associated with the event interrupts and
95 the second element is associated with the error interrupts.
97 - fsl,qman-channel-range
99 Value type: <prop-encoded-array>
100 Definition: Specifies the range of the available dedicated
101 channels in the FMan. The first cell specifies the beginning
102 of the range and the second cell specifies the number of
104 Further information available at:
105 "Work Queue (WQ) Channel Assignments in the QMan" section
106 in DPAA Reference Manual.
111 Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
113 - fsl,erratum-a050385
116 Definition: A boolean property. Indicates the presence of the
117 erratum A050385 which indicates that DMA transactions that are
118 split can result in a FMan lock.
120 =============================================================================
125 FMan Internal memory - shared between all the FMan modules.
126 It contains data structures that are common and written to or read by
128 FMan internal memory is split into the following parts:
129 Packet buffering (Tx/Rx FIFOs)
130 Frames internal context
136 Value type: <stringlist>
137 Definition: Must include "fsl,fman-muram"
141 Value type: <prop-encoded-array>
142 Definition: A standard property.
143 Specifies the multi-user memory offset and the size within
149 compatible = "fsl,fman-muram";
150 ranges = <0 0x000000 0x28000>;
153 =============================================================================
158 The Frame Manager (FMan) supports several types of hardware ports:
159 Ethernet receiver (RX)
160 Ethernet transmitter (TX)
161 Offline/Host command (O/H)
167 Value type: <stringlist>
168 Definition: A standard property.
169 Must include one of the following:
170 - "fsl,fman-v2-port-oh" for FManV2 OH ports
171 - "fsl,fman-v2-port-rx" for FManV2 RX ports
172 - "fsl,fman-v2-port-tx" for FManV2 TX ports
173 - "fsl,fman-v3-port-oh" for FManV3 OH ports
174 - "fsl,fman-v3-port-rx" for FManV3 RX ports
175 - "fsl,fman-v3-port-tx" for FManV3 TX ports
180 Definition: Specifies the hardware port id.
181 Each hardware port on the FMan has its own hardware PortID.
182 Super set of all hardware Port IDs available at FMan Reference
183 Manual under "FMan Hardware Ports in Freescale Devices" table.
185 Each hardware port is assigned a 4KB, port-specific page in
186 the FMan hardware port memory region (which is part of the
187 FMan memory map). The first 4 KB in the FMan hardware ports
188 memory region is used for what are called common registers.
189 The subsequent 63 4KB pages are allocated to the hardware
191 The page of a specific port is determined by the cell-index.
195 Value type: <prop-encoded-array>
196 Definition: There is one reg region describing the port
197 configuration registers.
202 Definition: The default port rate is 1G.
203 If this property exists, the port is s 10G port.
205 - fsl,fman-best-effort-port
208 Definition: Can be defined only if 10G-support is set.
209 This property marks a best-effort 10G port (10G port that
210 may not be capable of line rate).
216 compatible = "fsl,fman-v2-port-tx";
217 reg = <0xa8000 0x1000>;
222 compatible = "fsl,fman-v2-port-rx";
223 reg = <0x88000 0x1000>;
228 compatible = "fsl,fman-v2-port-oh";
229 reg = <0x81000 0x1000>;
232 =============================================================================
233 FMan dTSEC/XGEC/mEMAC Node
235 Refer to Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml
237 ============================================================================
240 Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
242 =============================================================================
247 The MDIO is a bus to which the PHY devices are connected.
253 Value type: <stringlist>
254 Definition: A standard property.
255 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
256 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
257 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
262 Value type: <prop-encoded-array>
263 Definition: A standard property.
267 Value type: <phandle>
268 Definition: A reference to the input clock of the controller
269 from which the MDC frequency is derived.
274 Definition: Specifies the external MDC frequency, in Hertz, to
275 be used. Requires that the input clock is specified in the
276 "clocks" property. See also: mdio.yaml.
280 Value type: <boolean>
281 Definition: Disable generation of preamble bits. See also:
285 Usage: required for external MDIO
286 Value type: <prop-encoded-array>
287 Definition: Event interrupt of external MDIO controller.
289 - fsl,fman-internal-mdio
290 Usage: required for internal MDIO
292 Definition: Fman has internal MDIO for internal PCS(Physical
293 Coding Sublayer) PHYs and external MDIO for external PHYs.
294 The settings and programming routines for internal/external
295 MDIO are different. Must be included for internal MDIO.
297 - fsl,erratum-a009885
299 Value type: <boolean>
300 Definition: Indicates the presence of the A009885
301 erratum describing that the contents of MDIO_DATA may
302 become corrupt unless it is read within 16 MDC cycles
303 of MDIO_CFG[BSY] being cleared, when performing an
306 - fsl,erratum-a011043
308 Value type: <boolean>
309 Definition: Indicates the presence of the A011043 erratum
310 describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
311 set when reading internal PCS registers. MDIO reads to
312 internal PCS registers may result in having the
313 MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
314 read data (MDIO_DATA[MDIO_DATA]) is correct.
315 Software may get false read error when reading internal
316 PCS registers through MDIO. As a workaround, all internal
317 MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
319 For internal PHY device on internal mdio bus, a PHY node should be created.
320 See the definition of the PHY node in booting-without-of.txt for an
321 example of how to define a PHY (Internal PHY has no interrupt line).
322 - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
323 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
324 PCS PHY addr must be '0'.
328 Example for FMan v2 external MDIO:
331 compatible = "fsl,fman-xmdio";
332 reg = <0xf1000 0x1000>;
333 interrupts = <101 2 0 0>;
336 Example for FMan v2 internal MDIO:
339 compatible = "fsl,fman-mdio";
340 reg = <0xe3120 0xee0>;
341 fsl,fman-internal-mdio;
345 device_type = "tbi-phy";
349 Example for FMan v3 internal MDIO:
352 compatible = "fsl,fman-memac-mdio";
353 reg = <0xf1000 0x1000>;
354 fsl,fman-internal-mdio;
356 pcsphy6: ethernet-phy@0 {
361 =============================================================================
365 #address-cells = <1>;
368 compatible = "fsl,fman"
369 ranges = <0 0x400000 0x100000>;
370 reg = <0x400000 0x100000>;
371 clocks = <&fman_clk>;
372 clock-names = "fmanclk";
376 fsl,qman-channel-range = <0x40 0xc>;
379 compatible = "fsl,fman-muram";
385 compatible = "fsl,fman-v2-port-oh";
386 reg = <0x81000 0x1000>;
391 compatible = "fsl,fman-v2-port-oh";
392 reg = <0x82000 0x1000>;
397 compatible = "fsl,fman-v2-port-oh";
398 reg = <0x83000 0x1000>;
403 compatible = "fsl,fman-v2-port-oh";
404 reg = <0x84000 0x1000>;
409 compatible = "fsl,fman-v2-port-oh";
410 reg = <0x85000 0x1000>;
415 compatible = "fsl,fman-v2-port-oh";
416 reg = <0x86000 0x1000>;
419 fman1_rx_0x8: port@88000 {
421 compatible = "fsl,fman-v2-port-rx";
422 reg = <0x88000 0x1000>;
425 fman1_rx_0x9: port@89000 {
427 compatible = "fsl,fman-v2-port-rx";
428 reg = <0x89000 0x1000>;
431 fman1_rx_0xa: port@8a000 {
433 compatible = "fsl,fman-v2-port-rx";
434 reg = <0x8a000 0x1000>;
437 fman1_rx_0xb: port@8b000 {
439 compatible = "fsl,fman-v2-port-rx";
440 reg = <0x8b000 0x1000>;
443 fman1_rx_0xc: port@8c000 {
445 compatible = "fsl,fman-v2-port-rx";
446 reg = <0x8c000 0x1000>;
449 fman1_rx_0x10: port@90000 {
451 compatible = "fsl,fman-v2-port-rx";
452 reg = <0x90000 0x1000>;
455 fman1_tx_0x28: port@a8000 {
457 compatible = "fsl,fman-v2-port-tx";
458 reg = <0xa8000 0x1000>;
461 fman1_tx_0x29: port@a9000 {
463 compatible = "fsl,fman-v2-port-tx";
464 reg = <0xa9000 0x1000>;
467 fman1_tx_0x2a: port@aa000 {
469 compatible = "fsl,fman-v2-port-tx";
470 reg = <0xaa000 0x1000>;
473 fman1_tx_0x2b: port@ab000 {
475 compatible = "fsl,fman-v2-port-tx";
476 reg = <0xab000 0x1000>;
479 fman1_tx_0x2c: port@ac0000 {
481 compatible = "fsl,fman-v2-port-tx";
482 reg = <0xac000 0x1000>;
485 fman1_tx_0x30: port@b0000 {
487 compatible = "fsl,fman-v2-port-tx";
488 reg = <0xb0000 0x1000>;
492 compatible = "fsl,fman-dtsec";
494 reg = <0xe0000 0x1000>;
495 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
496 tbi-handle = <&tbi5>;
500 compatible = "fsl,fman-dtsec";
502 reg = <0xe2000 0x1000>;
503 fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
504 tbi-handle = <&tbi6>;
508 compatible = "fsl,fman-dtsec";
510 reg = <0xe4000 0x1000>;
511 fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
512 tbi-handle = <&tbi7>;
516 compatible = "fsl,fman-dtsec";
518 reg = <0xe6000 0x1000>;
519 fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
520 tbi-handle = <&tbi8>;
524 compatible = "fsl,fman-dtsec";
526 reg = <0xf0000 0x1000>;
527 fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
528 tbi-handle = <&tbi9>;
532 compatible = "fsl,fman-xgec";
533 reg = <0xf0000 0x1000>;
534 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
538 compatible = "fsl,fman-ptp-timer";
539 reg = <0xfe000 0x1000>;
543 compatible = "fsl,fman-xmdio";
544 reg = <0xf1000 0x1000>;
545 interrupts = <101 2 0 0>;