1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Fast Ethernet Controller (FEC)
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
31 - const: fsl,imx25-fec
36 - const: fsl,imx27-fec
41 - const: fsl,imx6q-fec
45 - const: fsl,imx6sx-fec
47 - const: fsl,imx8mq-fec
48 - const: fsl,imx6sx-fec
55 - const: fsl,imx8mq-fec
56 - const: fsl,imx6sx-fec
58 - const: fsl,imx8qm-fec
59 - const: fsl,imx6sx-fec
64 - const: fsl,imx8qm-fec
65 - const: fsl,imx6sx-fec
69 - const: fsl,imx6ul-fec
70 - const: fsl,imx6q-fec
100 The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing.
101 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
102 The "ptp"(option), for IEEE1588 timer clock that requires the clock.
103 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
104 RGMII TXC clock or RMII reference clock. It depends on board design,
105 the clock is required if RGMII TXC and RMII reference clock source from
107 The "enet_out"(option), output clock for external device, like supply clock
108 for PHY. The clock is required if PHY clock source from SOC.
109 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
110 The clock is required if SoC RGMII enable clock delay.
130 local-mac-address: true
136 nvmem-cell-names: true
138 tx-internal-delay-ps:
141 rx-internal-delay-ps:
146 Regulator that powers the Ethernet PHY.
152 $ref: /schemas/types.yaml#/definitions/uint32
154 The property is valid for enet-avb IP, which supports hw multi queues.
155 Should specify the tx queue number, otherwise set tx queue number to 1.
159 $ref: /schemas/types.yaml#/definitions/uint32
161 The property is valid for enet-avb IP, which supports hw multi queues.
162 Should specify the rx queue number, otherwise set rx queue number to 1.
166 $ref: /schemas/types.yaml#/definitions/flag
168 If present, indicates that the hardware supports waking up via magic packet.
170 fsl,err006687-workaround-present:
171 $ref: /schemas/types.yaml#/definitions/flag
173 If present indicates that the system has the hardware workaround for
174 ERR006687 applied and does not need a software workaround.
177 $ref: /schemas/types.yaml#/definitions/phandle-array
180 - description: phandle to general purpose register node
181 - description: the gpr register offset for ENET stop request
182 - description: the gpr bit offset for ENET stop request
184 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>.
188 unevaluatedProperties: false
190 Specifies the mdio bus in the FEC, used as a container for phy nodes.
192 # Deprecated optional properties:
193 # To avoid these, create a phy node according to ethernet-phy.yaml in the same
194 # directory, and point the FEC's "phy-handle" property to it. Then use
195 # the phy's reset binding, again described by ethernet-phy.yaml.
200 Should specify the gpio for phy reset.
203 $ref: /schemas/types.yaml#/definitions/uint32
206 Reset duration in milliseconds. Should present only if property
207 "phy-reset-gpios" is available. Missing the property will have the
208 duration be 1 millisecond. Numbers greater than 1000 are invalid
209 and 1 millisecond will be used instead.
211 phy-reset-active-high:
215 If present then the reset sequence using the GPIO specified in the
216 "phy-reset-gpios" property is reversed (H=reset state, L=operation state).
218 phy-reset-post-delay:
219 $ref: /schemas/types.yaml#/definitions/uint32
222 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay
223 milliseconds will be observed after the phy-reset-gpios has been toggled.
224 Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms.
225 Other delays are invalid.
232 # FIXME: We had better set additionalProperties to false to avoid invalid or at
233 # least undocumented properties. However, PHY may have a deprecated option to
234 # place PHY OF properties in the MAC node, such as Micrel PHY, and we can find
235 # these boards which is based on i.MX6QDL.
236 unevaluatedProperties: false
241 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
242 reg = <0x83fec000 0x4000>;
245 phy-reset-gpios = <&gpio2 14 0>;
246 phy-supply = <®_fec_supply>;
250 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
251 reg = <0x83fed000 0x4000>;
254 phy-reset-gpios = <&gpio2 14 0>;
255 phy-supply = <®_fec_supply>;
256 phy-handle = <ðphy0>;
259 #address-cells = <1>;
262 ethphy0: ethernet-phy@0 {
263 compatible = "ethernet-phy-ieee802.3-c22";