1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
15 # the compatible, and second by using the node name if any. In our
16 # case, the node name is the one we want to match on, while the
17 # compatible is optional.
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
28 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32 - const: ethernet-phy-ieee802.3-c22
33 description: PHYs that implement IEEE802.3 clause 22
34 - const: ethernet-phy-ieee802.3-c45
35 description: PHYs that implement IEEE802.3 clause 45
36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
38 If the PHY reports an incorrect ID (or none at all) then the
39 compatible list may contain an entry with the correct PHY ID
41 The first group of digits is the 16 bit Phy Identifier 1
42 register, this is the chip vendor OUI bits 3:18. The
43 second group of digits is the Phy Identifier 2 register,
44 this is the chip vendor OUI bits 19:24, followed by 10
45 bits of a vendor specific ID.
47 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48 - const: ethernet-phy-ieee802.3-c22
50 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
51 - const: ethernet-phy-ieee802.3-c45
57 The ID number for the PHY.
78 Maximum PHY supported speed in Mbits / seconds.
80 phy-10base-t1l-2.4vpp:
82 tristate, request/disable 2.4 Vpp operating mode. The values are:
83 0: Disable 2.4 Vpp operating mode.
84 1: Request 2.4 Vpp operating mode from link partner.
85 Absence of this property will leave configuration to default values.
86 $ref: "/schemas/types.yaml#/definitions/uint32"
90 $ref: /schemas/types.yaml#/definitions/flag
92 If set, indicates the PHY device does not correctly release
93 the turn around line low at end of the control phase of the
97 $ref: /schemas/types.yaml#/definitions/flag
99 If set, indicates the PHY will swap the TX/RX lanes to
100 compensate for the board being designed with the lanes
103 enet-phy-lane-no-swap:
104 $ref: /schemas/types.yaml#/definitions/flag
106 If set, indicates that PHY will disable swap of the
107 TX/RX lanes. This property allows the PHY to work correcly after
108 e.g. wrong bootstrap configuration caused by issues in PCB
112 $ref: /schemas/types.yaml#/definitions/flag
114 Mark the corresponding energy efficient ethernet mode as
115 broken and request the ethernet to stop advertising it.
118 $ref: /schemas/types.yaml#/definitions/flag
120 Mark the corresponding energy efficient ethernet mode as
121 broken and request the ethernet to stop advertising it.
124 $ref: /schemas/types.yaml#/definitions/flag
126 Mark the corresponding energy efficient ethernet mode as
127 broken and request the ethernet to stop advertising it.
130 $ref: /schemas/types.yaml#/definitions/flag
132 Mark the corresponding energy efficient ethernet mode as
133 broken and request the ethernet to stop advertising it.
136 $ref: /schemas/types.yaml#/definitions/flag
138 Mark the corresponding energy efficient ethernet mode as
139 broken and request the ethernet to stop advertising it.
142 $ref: /schemas/types.yaml#/definitions/flag
144 Mark the corresponding energy efficient ethernet mode as
145 broken and request the ethernet to stop advertising it.
148 $ref: /schemas/types.yaml#/definitions/flag
150 If set, indicates that the PHY is integrated into the same
151 physical package as the Ethernet MAC. If needed, muxers
152 should be configured to ensure the integrated PHY is
153 used. The absence of this property indicates the muxers
154 should be configured so that the external PHY is used.
165 The GPIO phandle and specifier for the PHY reset signal.
169 Delay after the reset was asserted in microseconds. If this
170 property is missing the delay will be skipped.
174 Delay after the reset was deasserted in microseconds. If
175 this property is missing the delay will be skipped.
178 $ref: /schemas/types.yaml#/definitions/phandle
180 Specifies a reference to a node representing a SFP cage.
182 rx-internal-delay-ps:
184 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for
185 PHY's that have configurable RX internal delays. If this property is
186 present then the PHY applies the RX delay.
188 tx-internal-delay-ps:
190 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for
191 PHY's that have configurable TX internal delays. If this property is
192 present then the PHY applies the TX delay.
197 additionalProperties: true
202 #address-cells = <1>;
206 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
207 interrupt-parent = <&PIC>;
213 reset-gpios = <&gpio1 4 1>;
214 reset-assert-us = <1000>;
215 reset-deassert-us = <2000>;