1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
15 # the compatible, and second by using the node name if any. In our
16 # case, the node name is the one we want to match on, while the
17 # compatible is optional.
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
28 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32 - const: ethernet-phy-ieee802.3-c22
33 description: PHYs that implement IEEE802.3 clause 22
34 - const: ethernet-phy-ieee802.3-c45
35 description: PHYs that implement IEEE802.3 clause 45
36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
38 If the PHY reports an incorrect ID (or none at all) then the
39 compatible list may contain an entry with the correct PHY ID
41 The first group of digits is the 16 bit Phy Identifier 1
42 register, this is the chip vendor OUI bits 3:18. The
43 second group of digits is the Phy Identifier 2 register,
44 this is the chip vendor OUI bits 19:24, followed by 10
45 bits of a vendor specific ID.
47 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48 - const: ethernet-phy-ieee802.3-c22
50 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
51 - const: ethernet-phy-ieee802.3-c45
57 The ID number for the PHY.
78 Maximum PHY supported speed in Mbits / seconds.
81 $ref: /schemas/types.yaml#definitions/flag
83 If set, indicates the PHY device does not correctly release
84 the turn around line low at end of the control phase of the
88 $ref: /schemas/types.yaml#definitions/flag
90 If set, indicates the PHY will swap the TX/RX lanes to
91 compensate for the board being designed with the lanes
94 enet-phy-lane-no-swap:
95 $ref: /schemas/types.yaml#/definitions/flag
97 If set, indicates that PHY will disable swap of the
98 TX/RX lanes. This property allows the PHY to work correcly after
99 e.g. wrong bootstrap configuration caused by issues in PCB
103 $ref: /schemas/types.yaml#definitions/flag
105 Mark the corresponding energy efficient ethernet mode as
106 broken and request the ethernet to stop advertising it.
109 $ref: /schemas/types.yaml#definitions/flag
111 Mark the corresponding energy efficient ethernet mode as
112 broken and request the ethernet to stop advertising it.
115 $ref: /schemas/types.yaml#definitions/flag
117 Mark the corresponding energy efficient ethernet mode as
118 broken and request the ethernet to stop advertising it.
121 $ref: /schemas/types.yaml#definitions/flag
123 Mark the corresponding energy efficient ethernet mode as
124 broken and request the ethernet to stop advertising it.
127 $ref: /schemas/types.yaml#definitions/flag
129 Mark the corresponding energy efficient ethernet mode as
130 broken and request the ethernet to stop advertising it.
133 $ref: /schemas/types.yaml#definitions/flag
135 Mark the corresponding energy efficient ethernet mode as
136 broken and request the ethernet to stop advertising it.
139 $ref: /schemas/types.yaml#definitions/flag
141 If set, indicates that the PHY is integrated into the same
142 physical package as the Ethernet MAC. If needed, muxers
143 should be configured to ensure the integrated PHY is
144 used. The absence of this property indicates the muxers
145 should be configured so that the external PHY is used.
156 The GPIO phandle and specifier for the PHY reset signal.
160 Delay after the reset was asserted in microseconds. If this
161 property is missing the delay will be skipped.
165 Delay after the reset was deasserted in microseconds. If
166 this property is missing the delay will be skipped.
169 $ref: /schemas/types.yaml#definitions/phandle
171 Specifies a reference to a node representing a SFP cage.
173 rx-internal-delay-ps:
175 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for
176 PHY's that have configurable RX internal delays. If this property is
177 present then the PHY applies the RX delay.
179 tx-internal-delay-ps:
181 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for
182 PHY's that have configurable TX internal delays. If this property is
183 present then the PHY applies the TX delay.
188 additionalProperties: true
193 #address-cells = <1>;
197 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
198 interrupt-parent = <&PIC>;
204 reset-gpios = <&gpio1 4 1>;
205 reset-assert-us = <1000>;
206 reset-deassert-us = <2000>;