1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Controller Common Properties
10 - David S. Miller <davem@davemloft.net>
14 pattern: "^ethernet(@.*)?$"
17 $ref: /schemas/types.yaml#/definitions/string
18 description: Human readable label on a port of a box.
22 Specifies the MAC address that was assigned to the network device.
23 $ref: /schemas/types.yaml#/definitions/uint8-array
29 Specifies the MAC address that was last used by the boot
30 program; should be used in cases where the MAC address assigned
31 to the device by the boot program is different from the
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
38 $ref: /schemas/types.yaml#/definitions/uint32
40 Maximum transfer unit (IEEE defined MTU), rather than the
41 maximum frame size (there\'s contradiction in the Devicetree
45 $ref: /schemas/types.yaml#/definitions/uint32
47 Specifies maximum speed in Mbit/s supported by the device.
52 Reference to an nvmem node for the MAC address
59 Specifies interface type between the Ethernet device and a physical
62 # There is not a standard bus between the MAC and the PHY,
63 # something proprietary is being used to embed the PHY in the
78 # RX and TX delays are added by the MAC when required
81 # RGMII with internal RX and TX delays provided by the PHY,
82 # the MAC should not add the RX or TX delays in this case
85 # RGMII with internal RX delay provided by the PHY, the MAC
86 # should not add an RX delay in this case
89 # RGMII with internal TX delay provided by the PHY, the MAC
90 # should not add an TX delay in this case
102 # 10GBASE-KR, XFI, SFI
109 $ref: "#/properties/phy-connection-type"
112 $ref: /schemas/types.yaml#/definitions/phandle-array
116 Specifies a reference to a node representing a PCS PHY device on a MDIO
117 bus to link with an external PHY (phy-handle) if exists.
121 The name of each PCS in pcs-handle.
124 $ref: /schemas/types.yaml#/definitions/phandle
126 Specifies a reference to a node representing a PHY device.
129 $ref: "#/properties/phy-handle"
133 $ref: "#/properties/phy-handle"
137 $ref: /schemas/types.yaml#/definitions/uint32
139 The size of the controller\'s receive fifo in bytes. This is used
140 for components that can have configurable receive fifo sizes,
141 and is useful for determining certain configuration settings
142 such as flow control thresholds.
145 $ref: /schemas/types.yaml#/definitions/phandle
147 Specifies a reference to a node representing a SFP cage.
150 $ref: /schemas/types.yaml#/definitions/uint32
152 The size of the controller\'s transmit fifo in bytes. This
153 is used for components that can have configurable fifo sizes.
157 Specifies the PHY management type. If auto is set and fixed-link
158 is not specified, it uses MDIO for management.
159 $ref: /schemas/types.yaml#/definitions/string
167 - $ref: /schemas/types.yaml#/definitions/uint32-array
173 Emulated PHY ID, choose any but unique to the all
174 specified fixed-links
178 Duplex configuration. 0 for half duplex or 1 for
181 - enum: [10, 100, 1000, 2500, 10000]
183 Link speed in Mbits/sec.
187 Pause configuration. 0 for no pause, 1 for pause
191 Asymmetric pause configuration. 0 for no asymmetric
192 pause, 1 for asymmetric pause
194 additionalProperties: false
199 $ref: /schemas/types.yaml#/definitions/uint32
200 enum: [10, 100, 1000, 2500, 10000]
203 $ref: /schemas/types.yaml#/definitions/flag
205 Indicates that full-duplex is used. When absent, half
209 $ref: /schemas/types.yaml#/definitions/flag
211 Indicates that pause should be enabled.
214 $ref: /schemas/types.yaml#/definitions/flag
216 Indicates that asym_pause should be enabled.
221 GPIO to determine if the link is up
228 Describes the LEDs associated by Ethernet Controller.
229 These LEDs are not integrated in the PHY and PHY doesn't have any
230 control on them. Ethernet Controller regs are used to control
244 $ref: /schemas/leds/common.yaml#
250 This define the LED index in the PHY or the MAC. It's really
251 driver dependent and required for ports that define multiple
252 LED for the same port.
257 unevaluatedProperties: false
259 additionalProperties: false
262 pcs-handle-names: [pcs-handle]
276 rx-internal-delay-ps:
278 RGMII Receive Clock Delay defined in pico seconds. This is used for
279 controllers that have configurable RX internal delays. If this
280 property is present then the MAC applies the RX delay.
281 tx-internal-delay-ps:
283 RGMII Transmit Clock Delay defined in pico seconds. This is used for
284 controllers that have configurable TX internal delays. If this
285 property is present then the MAC applies the TX delay.
287 additionalProperties: true