1 * Allwinner sun8i GMAC ethernet controller
3 This device is a platform glue layer for stmmac.
4 Please see stmmac.txt for the other unchanged properties.
7 - compatible: must be one of the following string:
8 "allwinner,sun8i-a83t-emac"
9 "allwinner,sun8i-h3-emac"
10 "allwinner,sun8i-r40-gmac"
11 "allwinner,sun8i-v3s-emac"
12 "allwinner,sun50i-a64-emac"
13 - reg: address and length of the register for the device.
14 - interrupts: interrupt for the device
15 - interrupt-names: must be "macirq"
16 - clocks: A phandle to the reference clock for this device
17 - clock-names: must be "stmmaceth"
18 - resets: A phandle to the reset control for this device
19 - reset-names: must be "stmmaceth"
20 - phy-mode: See ethernet.txt
21 - phy-handle: See ethernet.txt
22 - syscon: A phandle to the device containing the EMAC or GMAC clock register
25 - allwinner,tx-delay-ps: TX clock delay chain value in ps.
26 Range is 0-700. Default is 0.
27 Unavailable for allwinner,sun8i-r40-gmac
28 - allwinner,rx-delay-ps: RX clock delay chain value in ps.
29 Range is 0-3100. Default is 0.
30 Range is 0-700 for allwinner,sun8i-r40-gmac
31 Both delay properties need to be a multiple of 100. They control the
32 clock delay for external RGMII PHY. They do not apply to the internal
33 PHY or external non-RGMII PHYs.
35 Optional properties for the following compatibles:
36 - "allwinner,sun8i-h3-emac",
37 - "allwinner,sun8i-v3s-emac":
38 - allwinner,leds-active-low: EPHY LEDs are active low
40 Required child node of emac:
41 - mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
43 Required properties of the mdio node:
44 - #address-cells: shall be 1
45 - #size-cells: shall be 0
47 The device node referenced by "phy" or "phy-handle" must be a child node
48 of the mdio node. See phy.txt for the generic PHY bindings.
50 The following compatibles require that the emac node have a mdio-mux child
51 node called "mdio-mux":
52 - "allwinner,sun8i-h3-emac"
53 - "allwinner,sun8i-v3s-emac":
54 Required properties for the mdio-mux node:
55 - compatible = "allwinner,sun8i-h3-mdio-mux"
56 - mdio-parent-bus: a phandle to EMAC mdio
57 - one child mdio for the integrated mdio with the compatible
58 "allwinner,sun8i-h3-mdio-internal"
59 - one child mdio for the external mdio if present (V3s have none)
60 Required properties for the mdio-mux children node:
61 - reg: 1 for internal MDIO bus, 2 for external MDIO bus
63 The following compatibles require a PHY node representing the integrated
64 PHY, under the integrated MDIO bus node if an mdio-mux node is used:
65 - "allwinner,sun8i-h3-emac",
66 - "allwinner,sun8i-v3s-emac":
68 Additional information regarding generic multiplexer properties can be found
69 at Documentation/devicetree/bindings/net/mdio-mux.txt
71 Required properties of the integrated phy node:
72 - clocks: a phandle to the reference clock for the EPHY
73 - resets: a phandle to the reset control for the EPHY
74 - Must be a child of the integrated mdio
76 Example with integrated PHY:
77 emac: ethernet@1c0b000 {
78 compatible = "allwinner,sun8i-h3-emac";
80 reg = <0x01c0b000 0x104>;
81 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-names = "macirq";
83 resets = <&ccu RST_BUS_EMAC>;
84 reset-names = "stmmaceth";
85 clocks = <&ccu CLK_BUS_EMAC>;
86 clock-names = "stmmaceth";
88 phy-handle = <&int_mii_phy>;
90 allwinner,leds-active-low;
95 compatible = "snps,dwmac-mdio";
99 compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
100 #address-cells = <1>;
103 mdio-parent-bus = <&mdio>;
106 compatible = "allwinner,sun8i-h3-mdio-internal";
108 #address-cells = <1>;
110 int_mii_phy: ethernet-phy@1 {
112 clocks = <&ccu CLK_BUS_EPHY>;
113 resets = <&ccu RST_BUS_EPHY>;
119 #address-cells = <1>;
125 Example with external PHY:
126 emac: ethernet@1c0b000 {
127 compatible = "allwinner,sun8i-h3-emac";
129 reg = <0x01c0b000 0x104>;
130 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
131 interrupt-names = "macirq";
132 resets = <&ccu RST_BUS_EMAC>;
133 reset-names = "stmmaceth";
134 clocks = <&ccu CLK_BUS_EMAC>;
135 clock-names = "stmmaceth";
137 phy-handle = <&ext_rgmii_phy>;
139 allwinner,leds-active-low;
142 #address-cells = <1>;
144 compatible = "snps,dwmac-mdio";
148 compatible = "allwinner,sun8i-h3-mdio-mux";
149 #address-cells = <1>;
152 mdio-parent-bus = <&mdio>;
155 compatible = "allwinner,sun8i-h3-mdio-internal";
157 #address-cells = <1>;
159 int_mii_phy: ethernet-phy@1 {
161 clocks = <&ccu CLK_BUS_EPHY>;
162 resets = <&ccu RST_BUS_EPHY>;
167 #address-cells = <1>;
169 ext_rgmii_phy: ethernet-phy@1 {
176 Example with SoC without integrated PHY
178 emac: ethernet@1c0b000 {
179 compatible = "allwinner,sun8i-a83t-emac";
181 reg = <0x01c0b000 0x104>;
182 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
183 interrupt-names = "macirq";
184 resets = <&ccu RST_BUS_EMAC>;
185 reset-names = "stmmaceth";
186 clocks = <&ccu CLK_BUS_EMAC>;
187 clock-names = "stmmaceth";
189 phy-handle = <&ext_rgmii_phy>;
193 compatible = "snps,dwmac-mdio";
194 #address-cells = <1>;
196 ext_rgmii_phy: ethernet-phy@1 {