1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/dsa/realtek.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek switches for unmanaged switches
13 - Linus Walleij <linus.walleij@linaro.org>
16 Realtek advertises these chips as fast/gigabit switches or unmanaged
17 switches. They can be controlled using different interfaces, like SMI,
20 The SMI "Simple Management Interface" is a two-wire protocol using
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
22 not use the MDIO protocol. This binding defines how to specify the
23 SMI-based Realtek devices. The realtek-smi driver is a platform driver
24 and it must be inserted inside a platform node.
26 The MDIO-connected switches use MDIO protocol to access their registers.
27 The realtek-mdio driver is an MDIO driver and it must be inserted inside
30 The compatible string is only used to identify which (silicon) family the
31 switch belongs to. Roughly speaking, a family is any set of Realtek switches
32 whose chip identification register(s) have a common location and semantics.
33 The different models in a given family can be automatically disambiguated by
34 parsing the chip identification register(s) according to the given family,
35 avoiding the need for a unique compatible string for each model.
44 Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
45 RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
46 RTL8367SB, RTL8370MB, RTL8310SR
48 Use with models RTL8366RB, RTL8366S
51 description: GPIO line for the MDC clock line.
55 description: GPIO line for the MDIO data line.
59 description: GPIO to be used to reset the whole device
65 if the LED drivers are not used in the hardware design,
66 this will disable them so they are not turned on
72 This defines an interrupt controller with an IRQ line (typically
73 a GPIO) that will demultiplex and handle the interrupt from the single
74 interrupt line coming out of one of the Realtek switch chips. It most
75 importantly provides link up/down interrupts to the PHY blocks inside
80 interrupt-controller: true
85 A single IRQ line from the switch, either active LOW or HIGH
94 - interrupt-controller
99 $ref: /schemas/net/mdio.yaml#
100 unevaluatedProperties: false
104 const: realtek,smi-mdio
111 $ref: /schemas/spi/spi-peripheral-props.yaml#
138 unevaluatedProperties: false
142 #include <dt-bindings/gpio/gpio.h>
143 #include <dt-bindings/interrupt-controller/irq.h>
147 compatible = "realtek,rtl8366rb";
148 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
149 mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
150 mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
151 reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
153 switch_intc1: interrupt-controller {
154 /* GPIO 15 provides the interrupt */
155 interrupt-parent = <&gpio0>;
156 interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
157 interrupt-controller;
158 #address-cells = <0>;
159 #interrupt-cells = <1>;
163 #address-cells = <1>;
168 phy-handle = <&phy0>;
173 phy-handle = <&phy1>;
178 phy-handle = <&phy2>;
183 phy-handle = <&phy3>;
188 phy-handle = <&phy4>;
203 compatible = "realtek,smi-mdio";
204 #address-cells = <1>;
207 phy0: ethernet-phy@0 {
209 interrupt-parent = <&switch_intc1>;
212 phy1: ethernet-phy@1 {
214 interrupt-parent = <&switch_intc1>;
217 phy2: ethernet-phy@2 {
219 interrupt-parent = <&switch_intc1>;
222 phy3: ethernet-phy@3 {
224 interrupt-parent = <&switch_intc1>;
227 phy4: ethernet-phy@4 {
229 interrupt-parent = <&switch_intc1>;
237 #include <dt-bindings/gpio/gpio.h>
238 #include <dt-bindings/interrupt-controller/irq.h>
242 compatible = "realtek,rtl8365mb";
243 mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
244 mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
245 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
247 switch_intc2: interrupt-controller {
248 interrupt-parent = <&gpio5>;
249 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
250 interrupt-controller;
251 #address-cells = <0>;
252 #interrupt-cells = <1>;
256 #address-cells = <1>;
261 phy-handle = <ðphy0>;
266 phy-handle = <ðphy1>;
271 phy-handle = <ðphy2>;
276 phy-handle = <ðphy3>;
283 tx-internal-delay-ps = <2000>;
284 rx-internal-delay-ps = <2000>;
295 compatible = "realtek,smi-mdio";
296 #address-cells = <1>;
299 ethphy0: ethernet-phy@0 {
301 interrupt-parent = <&switch_intc2>;
304 ethphy1: ethernet-phy@1 {
306 interrupt-parent = <&switch_intc2>;
309 ethphy2: ethernet-phy@2 {
311 interrupt-parent = <&switch_intc2>;
314 ethphy3: ethernet-phy@3 {
316 interrupt-parent = <&switch_intc2>;
324 #include <dt-bindings/gpio/gpio.h>
325 #include <dt-bindings/interrupt-controller/irq.h>
328 #address-cells = <1>;
332 compatible = "realtek,rtl8365mb";
335 reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
337 switch_intc3: interrupt-controller {
338 interrupt-parent = <&gpio0>;
339 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
340 interrupt-controller;
341 #address-cells = <0>;
342 #interrupt-cells = <1>;
346 #address-cells = <1>;
376 ethernet = <ðernet>;
378 tx-internal-delay-ps = <2000>;
379 rx-internal-delay-ps = <0>;