Documentation/devicetree/bindings/net/dsa/realtek.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/dsa/realtek.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Realtek switches for unmanaged switches
   8
   9 allOf:
  10   - $ref: dsa.yaml#
  11
  12 maintainers:
  13   - Linus Walleij <linus.walleij@linaro.org>
  14
  15 description:
  16   Realtek advertises these chips as fast/gigabit switches or unmanaged
  17   switches. They can be controlled using different interfaces, like SMI,
  18   MDIO or SPI.
  19
  20   The SMI "Simple Management Interface" is a two-wire protocol using
  21   bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
  22   not use the MDIO protocol. This binding defines how to specify the
  23   SMI-based Realtek devices. The realtek-smi driver is a platform driver
  24   and it must be inserted inside a platform node.
  25
  26   The MDIO-connected switches use MDIO protocol to access their registers.
  27   The realtek-mdio driver is an MDIO driver and it must be inserted inside
  28   an MDIO node.
  29
  30   The compatible string is only used to identify which (silicon) family the
  31   switch belongs to. Roughly speaking, a family is any set of Realtek switches
  32   whose chip identification register(s) have a common location and semantics.
  33   The different models in a given family can be automatically disambiguated by
  34   parsing the chip identification register(s) according to the given family,
  35   avoiding the need for a unique compatible string for each model.
  36
  37 properties:
  38   compatible:
  39     enum:
  40       - realtek,rtl8365mb
  41       - realtek,rtl8366rb
  42     description: |
  43       realtek,rtl8365mb:
  44         Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB,
  45         RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S,
  46         RTL8367SB, RTL8370MB, RTL8310SR
  47       realtek,rtl8366rb:
  48         Use with models RTL8366RB, RTL8366S
  49
  50   mdc-gpios:
  51     description: GPIO line for the MDC clock line.
  52     maxItems: 1
  53
  54   mdio-gpios:
  55     description: GPIO line for the MDIO data line.
  56     maxItems: 1
  57
  58   reset-gpios:
  59     description: GPIO to be used to reset the whole device
  60     maxItems: 1
  61
  62   realtek,disable-leds:
  63     type: boolean
  64     description: |
  65       if the LED drivers are not used in the hardware design,
  66       this will disable them so they are not turned on
  67       and wasting power.
  68
  69   interrupt-controller:
  70     type: object
  71     description: |
  72       This defines an interrupt controller with an IRQ line (typically
  73       a GPIO) that will demultiplex and handle the interrupt from the single
  74       interrupt line coming out of one of the Realtek switch chips. It most
  75       importantly provides link up/down interrupts to the PHY blocks inside
  76       the ASIC.
  77
  78     properties:
  79
  80       interrupt-controller: true
  81
  82       interrupts:
  83         maxItems: 1
  84         description:
  85           A single IRQ line from the switch, either active LOW or HIGH
  86
  87       '#address-cells':
  88         const: 0
  89
  90       '#interrupt-cells':
  91         const: 1
  92
  93     required:
  94       - interrupt-controller
  95       - '#address-cells'
  96       - '#interrupt-cells'
  97
  98   mdio:
  99     $ref: /schemas/net/mdio.yaml#
 100     unevaluatedProperties: false
 101
 102     properties:
 103       compatible:
 104         const: realtek,smi-mdio
 105
 106 if:
 107   required:
 108     - reg
 109
 110 then:
 111   $ref: /schemas/spi/spi-peripheral-props.yaml#
 112   not:
 113     required:
 114       - mdc-gpios
 115       - mdio-gpios
 116       - mdio
 117
 118   properties:
 119     mdc-gpios: false
 120     mdio-gpios: false
 121     mdio: false
 122
 123 else:
 124   required:
 125     - mdc-gpios
 126     - mdio-gpios
 127     - mdio
 128     - reset-gpios
 129
 130 required:
 131   - compatible
 132
 133     #  - mdc-gpios
 134     #  - mdio-gpios
 135     #  - reset-gpios
 136     #  - mdio
 137
 138 unevaluatedProperties: false
 139
 140 examples:
 141   - |
 142     #include <dt-bindings/gpio/gpio.h>
 143     #include <dt-bindings/interrupt-controller/irq.h>
 144
 145     platform {
 146             switch {
 147                     compatible = "realtek,rtl8366rb";
 148                     /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
 149                     mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
 150                     mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
 151                     reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
 152
 153                     switch_intc1: interrupt-controller {
 154                             /* GPIO 15 provides the interrupt */
 155                             interrupt-parent = <&gpio0>;
 156                             interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
 157                             interrupt-controller;
 158                             #address-cells = <0>;
 159                             #interrupt-cells = <1>;
 160                     };
 161
 162                     ports {
 163                             #address-cells = <1>;
 164                             #size-cells = <0>;
 165                             port@0 {
 166                                     reg = <0>;
 167                                     label = "lan0";
 168                                     phy-handle = <&phy0>;
 169                             };
 170                             port@1 {
 171                                     reg = <1>;
 172                                     label = "lan1";
 173                                     phy-handle = <&phy1>;
 174                             };
 175                             port@2 {
 176                                     reg = <2>;
 177                                     label = "lan2";
 178                                     phy-handle = <&phy2>;
 179                             };
 180                             port@3 {
 181                                     reg = <3>;
 182                                     label = "lan3";
 183                                     phy-handle = <&phy3>;
 184                             };
 185                             port@4 {
 186                                     reg = <4>;
 187                                     label = "wan";
 188                                     phy-handle = <&phy4>;
 189                             };
 190                             port@5 {
 191                                     reg = <5>;
 192                                     ethernet = <&gmac0>;
 193                                     phy-mode = "rgmii";
 194                                     fixed-link {
 195                                             speed = <1000>;
 196                                             full-duplex;
 197                                     };
 198                             };
 199                     };
 200
 201                     mdio {
 202                             compatible = "realtek,smi-mdio";
 203                             #address-cells = <1>;
 204                             #size-cells = <0>;
 205
 206                             phy0: ethernet-phy@0 {
 207                                     reg = <0>;
 208                                     interrupt-parent = <&switch_intc1>;
 209                                     interrupts = <0>;
 210                             };
 211                             phy1: ethernet-phy@1 {
 212                                     reg = <1>;
 213                                     interrupt-parent = <&switch_intc1>;
 214                                     interrupts = <1>;
 215                             };
 216                             phy2: ethernet-phy@2 {
 217                                     reg = <2>;
 218                                     interrupt-parent = <&switch_intc1>;
 219                                     interrupts = <2>;
 220                             };
 221                             phy3: ethernet-phy@3 {
 222                                     reg = <3>;
 223                                     interrupt-parent = <&switch_intc1>;
 224                                     interrupts = <3>;
 225                             };
 226                             phy4: ethernet-phy@4 {
 227                                     reg = <4>;
 228                                     interrupt-parent = <&switch_intc1>;
 229                                     interrupts = <12>;
 230                             };
 231                     };
 232             };
 233     };
 234
 235   - |
 236     #include <dt-bindings/gpio/gpio.h>
 237     #include <dt-bindings/interrupt-controller/irq.h>
 238
 239     platform {
 240             switch {
 241                     compatible = "realtek,rtl8365mb";
 242                     mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
 243                     mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
 244                     reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 245
 246                     switch_intc2: interrupt-controller {
 247                             interrupt-parent = <&gpio5>;
 248                             interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
 249                             interrupt-controller;
 250                             #address-cells = <0>;
 251                             #interrupt-cells = <1>;
 252                     };
 253
 254                     ports {
 255                             #address-cells = <1>;
 256                             #size-cells = <0>;
 257                             port@0 {
 258                                     reg = <0>;
 259                                     label = "swp0";
 260                                     phy-handle = <&ethphy0>;
 261                             };
 262                             port@1 {
 263                                     reg = <1>;
 264                                     label = "swp1";
 265                                     phy-handle = <&ethphy1>;
 266                             };
 267                             port@2 {
 268                                     reg = <2>;
 269                                     label = "swp2";
 270                                     phy-handle = <&ethphy2>;
 271                             };
 272                             port@3 {
 273                                     reg = <3>;
 274                                     label = "swp3";
 275                                     phy-handle = <&ethphy3>;
 276                             };
 277                             port@6 {
 278                                     reg = <6>;
 279                                     ethernet = <&fec1>;
 280                                     phy-mode = "rgmii";
 281                                     tx-internal-delay-ps = <2000>;
 282                                     rx-internal-delay-ps = <2000>;
 283
 284                                     fixed-link {
 285                                             speed = <1000>;
 286                                             full-duplex;
 287                                             pause;
 288                                     };
 289                             };
 290                     };
 291
 292                     mdio {
 293                             compatible = "realtek,smi-mdio";
 294                             #address-cells = <1>;
 295                             #size-cells = <0>;
 296
 297                             ethphy0: ethernet-phy@0 {
 298                                     reg = <0>;
 299                                     interrupt-parent = <&switch_intc2>;
 300                                     interrupts = <0>;
 301                             };
 302                             ethphy1: ethernet-phy@1 {
 303                                     reg = <1>;
 304                                     interrupt-parent = <&switch_intc2>;
 305                                     interrupts = <1>;
 306                             };
 307                             ethphy2: ethernet-phy@2 {
 308                                     reg = <2>;
 309                                     interrupt-parent = <&switch_intc2>;
 310                                     interrupts = <2>;
 311                             };
 312                             ethphy3: ethernet-phy@3 {
 313                                     reg = <3>;
 314                                     interrupt-parent = <&switch_intc2>;
 315                                     interrupts = <3>;
 316                             };
 317                     };
 318             };
 319     };
 320
 321   - |
 322     #include <dt-bindings/gpio/gpio.h>
 323     #include <dt-bindings/interrupt-controller/irq.h>
 324
 325     mdio {
 326             #address-cells = <1>;
 327             #size-cells = <0>;
 328
 329             switch@29 {
 330                     compatible = "realtek,rtl8365mb";
 331                     reg = <29>;
 332
 333                     reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
 334
 335                     switch_intc3: interrupt-controller {
 336                             interrupt-parent = <&gpio0>;
 337                             interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 338                             interrupt-controller;
 339                             #address-cells = <0>;
 340                             #interrupt-cells = <1>;
 341                     };
 342
 343                     ports {
 344                             #address-cells = <1>;
 345                             #size-cells = <0>;
 346
 347                             port@0 {
 348                                     reg = <0>;
 349                                     label = "lan4";
 350                             };
 351
 352                             port@1 {
 353                                     reg = <1>;
 354                                     label = "lan3";
 355                             };
 356
 357                             port@2 {
 358                                     reg = <2>;
 359                                     label = "lan2";
 360                             };
 361
 362                             port@3 {
 363                                     reg = <3>;
 364                                     label = "lan1";
 365                             };
 366
 367                             port@4 {
 368                                     reg = <4>;
 369                                     label = "wan";
 370                             };
 371
 372                             port@7 {
 373                                     reg = <7>;
 374                                     ethernet = <&ethernet>;
 375                                     phy-mode = "rgmii";
 376                                     tx-internal-delay-ps = <2000>;
 377                                     rx-internal-delay-ps = <0>;
 378
 379                                     fixed-link {
 380                                             speed = <1000>;
 381                                             full-duplex;
 382                                     };
 383                             };
 384                     };
 385             };
 386       };