Documentation/devicetree/bindings/net/dsa/qca8k.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Atheros QCA83xx switch family
   8
   9 maintainers:
  10   - John Crispin <john@phrozen.org>
  11
  12 description:
  13   If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
  14   describing a port needs to have a valid phandle referencing the internal PHY
  15   it is connected to. This is because there is no N:N mapping of port and PHY
  16   ID. To declare the internal mdio-bus configuration, declare an MDIO node in
  17   the switch node and declare the phandle for the port, referencing the internal
  18   PHY it is connected to. In this config, an internal mdio-bus is registered and
  19   the MDIO master is used for communication. Mixed external and internal
  20   mdio-bus configurations are not supported by the hardware.
  21
  22 properties:
  23   compatible:
  24     oneOf:
  25       - enum:
  26           - qca,qca8327
  27           - qca,qca8328
  28           - qca,qca8334
  29           - qca,qca8337
  30     description: |
  31       qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
  32       qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
  33       qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
  34       qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
  35
  36   reg:
  37     maxItems: 1
  38
  39   reset-gpios:
  40     description:
  41       GPIO to be used to reset the whole device
  42     maxItems: 1
  43
  44   qca,ignore-power-on-sel:
  45     $ref: /schemas/types.yaml#/definitions/flag
  46     description:
  47       Ignore power-on pin strapping to configure LED open-drain or EEPROM
  48       presence. This is needed for devices with incorrect configuration or when
  49       the OEM has decided not to use pin strapping and falls back to SW regs.
  50
  51   qca,led-open-drain:
  52     $ref: /schemas/types.yaml#/definitions/flag
  53     description:
  54       Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
  55       be set, otherwise the driver will fail at probe. This is required if the
  56       OEM does not use pin strapping to set this mode and prefers to set it
  57       using SW regs. The pin strappings related to LED open-drain mode are
  58       B68 on the QCA832x and B49 on the QCA833x.
  59
  60   mdio:
  61     $ref: /schemas/net/mdio.yaml#
  62     unevaluatedProperties: false
  63     description: Qca8k switch have an internal mdio to access switch port.
  64                  If this is not present, the legacy mapping is used and the
  65                  internal mdio access is used.
  66                  With the legacy mapping the reg corresponding to the internal
  67                  mdio is the switch reg with an offset of -1.
  68
  69 patternProperties:
  70   "^(ethernet-)?ports$":
  71     type: object
  72     properties:
  73       '#address-cells':
  74         const: 1
  75       '#size-cells':
  76         const: 0
  77
  78     patternProperties:
  79       "^(ethernet-)?port@[0-6]$":
  80         type: object
  81         description: Ethernet switch ports
  82
  83         $ref: dsa-port.yaml#
  84
  85         properties:
  86           qca,sgmii-rxclk-falling-edge:
  87             $ref: /schemas/types.yaml#/definitions/flag
  88             description:
  89               Set the receive clock phase to falling edge. Mostly commonly used on
  90               the QCA8327 with CPU port 0 set to SGMII.
  91
  92           qca,sgmii-txclk-falling-edge:
  93             $ref: /schemas/types.yaml#/definitions/flag
  94             description:
  95               Set the transmit clock phase to falling edge.
  96
  97           qca,sgmii-enable-pll:
  98             $ref: /schemas/types.yaml#/definitions/flag
  99             description:
 100               For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
 101               Signal Detection. On the QCA8327 this should not be enabled, otherwise
 102               the SGMII port will not initialize. When used on the QCA8337, revision 3
 103               or greater, a warning will be displayed. When the CPU port is set to
 104               SGMII on the QCA8337, it is advised to set this unless a communication
 105               issue is observed.
 106
 107         unevaluatedProperties: false
 108
 109 oneOf:
 110   - required:
 111       - ports
 112   - required:
 113       - ethernet-ports
 114
 115 required:
 116   - compatible
 117   - reg
 118
 119 additionalProperties: true
 120
 121 examples:
 122   - |
 123     #include <dt-bindings/gpio/gpio.h>
 124
 125     mdio {
 126         #address-cells = <1>;
 127         #size-cells = <0>;
 128
 129         external_phy_port1: ethernet-phy@0 {
 130             reg = <0>;
 131         };
 132
 133         external_phy_port2: ethernet-phy@1 {
 134             reg = <1>;
 135         };
 136
 137         external_phy_port3: ethernet-phy@2 {
 138             reg = <2>;
 139         };
 140
 141         external_phy_port4: ethernet-phy@3 {
 142             reg = <3>;
 143         };
 144
 145         external_phy_port5: ethernet-phy@4 {
 146             reg = <4>;
 147         };
 148
 149         switch@10 {
 150             compatible = "qca,qca8337";
 151             #address-cells = <1>;
 152             #size-cells = <0>;
 153             reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 154             reg = <0x10>;
 155
 156             ports {
 157                 #address-cells = <1>;
 158                 #size-cells = <0>;
 159
 160                 port@0 {
 161                     reg = <0>;
 162                     label = "cpu";
 163                     ethernet = <&gmac1>;
 164                     phy-mode = "rgmii";
 165
 166                     fixed-link {
 167                         speed = <1000>;
 168                         full-duplex;
 169                     };
 170                 };
 171
 172                 port@1 {
 173                     reg = <1>;
 174                     label = "lan1";
 175                     phy-handle = <&external_phy_port1>;
 176                 };
 177
 178                 port@2 {
 179                     reg = <2>;
 180                     label = "lan2";
 181                     phy-handle = <&external_phy_port2>;
 182                 };
 183
 184                 port@3 {
 185                     reg = <3>;
 186                     label = "lan3";
 187                     phy-handle = <&external_phy_port3>;
 188                 };
 189
 190                 port@4 {
 191                     reg = <4>;
 192                     label = "lan4";
 193                     phy-handle = <&external_phy_port4>;
 194                 };
 195
 196                 port@5 {
 197                     reg = <5>;
 198                     label = "wan";
 199                     phy-handle = <&external_phy_port5>;
 200                 };
 201             };
 202         };
 203     };
 204   - |
 205     #include <dt-bindings/gpio/gpio.h>
 206
 207     mdio {
 208         #address-cells = <1>;
 209         #size-cells = <0>;
 210
 211         switch@10 {
 212             compatible = "qca,qca8337";
 213             #address-cells = <1>;
 214             #size-cells = <0>;
 215             reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 216             reg = <0x10>;
 217
 218             ports {
 219                 #address-cells = <1>;
 220                 #size-cells = <0>;
 221
 222                 port@0 {
 223                     reg = <0>;
 224                     label = "cpu";
 225                     ethernet = <&gmac1>;
 226                     phy-mode = "rgmii";
 227
 228                     fixed-link {
 229                         speed = <1000>;
 230                         full-duplex;
 231                     };
 232                 };
 233
 234                 port@1 {
 235                     reg = <1>;
 236                     label = "lan1";
 237                     phy-mode = "internal";
 238                     phy-handle = <&internal_phy_port1>;
 239                 };
 240
 241                 port@2 {
 242                     reg = <2>;
 243                     label = "lan2";
 244                     phy-mode = "internal";
 245                     phy-handle = <&internal_phy_port2>;
 246                 };
 247
 248                 port@3 {
 249                     reg = <3>;
 250                     label = "lan3";
 251                     phy-mode = "internal";
 252                     phy-handle = <&internal_phy_port3>;
 253                 };
 254
 255                 port@4 {
 256                     reg = <4>;
 257                     label = "lan4";
 258                     phy-mode = "internal";
 259                     phy-handle = <&internal_phy_port4>;
 260                 };
 261
 262                 port@5 {
 263                     reg = <5>;
 264                     label = "wan";
 265                     phy-mode = "internal";
 266                     phy-handle = <&internal_phy_port5>;
 267                 };
 268
 269                 port@6 {
 270                     reg = <0>;
 271                     label = "cpu";
 272                     ethernet = <&gmac1>;
 273                     phy-mode = "sgmii";
 274
 275                     qca,sgmii-rxclk-falling-edge;
 276
 277                     fixed-link {
 278                         speed = <1000>;
 279                         full-duplex;
 280                     };
 281                 };
 282             };
 283
 284             mdio {
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287
 288                 internal_phy_port1: ethernet-phy@0 {
 289                     reg = <0>;
 290                 };
 291
 292                 internal_phy_port2: ethernet-phy@1 {
 293                     reg = <1>;
 294                 };
 295
 296                 internal_phy_port3: ethernet-phy@2 {
 297                     reg = <2>;
 298                 };
 299
 300                 internal_phy_port4: ethernet-phy@3 {
 301                     reg = <3>;
 302                 };
 303
 304                 internal_phy_port5: ethernet-phy@4 {
 305                     reg = <4>;
 306                 };
 307             };
 308         };
 309     };