Documentation/devicetree/bindings/net/dsa/qca8k.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/dsa/qca8k.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Atheros QCA83xx switch family
   8
   9 maintainers:
  10   - John Crispin <john@phrozen.org>
  11
  12 description:
  13   If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
  14   describing a port needs to have a valid phandle referencing the internal PHY
  15   it is connected to. This is because there is no N:N mapping of port and PHY
  16   ID. To declare the internal mdio-bus configuration, declare an MDIO node in
  17   the switch node and declare the phandle for the port, referencing the internal
  18   PHY it is connected to. In this config, an internal mdio-bus is registered and
  19   the MDIO master is used for communication. Mixed external and internal
  20   mdio-bus configurations are not supported by the hardware.
  21   Each phy has at most 3 LEDs connected and can be declared
  22   using the standard LEDs structure.
  23
  24 properties:
  25   compatible:
  26     oneOf:
  27       - enum:
  28           - qca,qca8327
  29           - qca,qca8328
  30           - qca,qca8334
  31           - qca,qca8337
  32     description: |
  33       qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
  34       qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
  35       qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
  36       qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
  37
  38   reg:
  39     maxItems: 1
  40
  41   reset-gpios:
  42     description:
  43       GPIO to be used to reset the whole device
  44     maxItems: 1
  45
  46   qca,ignore-power-on-sel:
  47     $ref: /schemas/types.yaml#/definitions/flag
  48     description:
  49       Ignore power-on pin strapping to configure LED open-drain or EEPROM
  50       presence. This is needed for devices with incorrect configuration or when
  51       the OEM has decided not to use pin strapping and falls back to SW regs.
  52
  53   qca,led-open-drain:
  54     $ref: /schemas/types.yaml#/definitions/flag
  55     description:
  56       Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
  57       be set, otherwise the driver will fail at probe. This is required if the
  58       OEM does not use pin strapping to set this mode and prefers to set it
  59       using SW regs. The pin strappings related to LED open-drain mode are
  60       B68 on the QCA832x and B49 on the QCA833x.
  61
  62   mdio:
  63     $ref: /schemas/net/mdio.yaml#
  64     unevaluatedProperties: false
  65     description: Qca8k switch have an internal mdio to access switch port.
  66                  If this is not present, the legacy mapping is used and the
  67                  internal mdio access is used.
  68                  With the legacy mapping the reg corresponding to the internal
  69                  mdio is the switch reg with an offset of -1.
  70
  71 $ref: dsa.yaml#
  72
  73 patternProperties:
  74   "^(ethernet-)?ports$":
  75     type: object
  76     additionalProperties: true
  77     patternProperties:
  78       "^(ethernet-)?port@[0-6]$":
  79         type: object
  80         description: Ethernet switch ports
  81
  82         $ref: dsa-port.yaml#
  83
  84         properties:
  85           qca,sgmii-rxclk-falling-edge:
  86             $ref: /schemas/types.yaml#/definitions/flag
  87             description:
  88               Set the receive clock phase to falling edge. Mostly commonly used on
  89               the QCA8327 with CPU port 0 set to SGMII.
  90
  91           qca,sgmii-txclk-falling-edge:
  92             $ref: /schemas/types.yaml#/definitions/flag
  93             description:
  94               Set the transmit clock phase to falling edge.
  95
  96           qca,sgmii-enable-pll:
  97             $ref: /schemas/types.yaml#/definitions/flag
  98             description:
  99               For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
 100               Signal Detection. On the QCA8327 this should not be enabled, otherwise
 101               the SGMII port will not initialize. When used on the QCA8337, revision 3
 102               or greater, a warning will be displayed. When the CPU port is set to
 103               SGMII on the QCA8337, it is advised to set this unless a communication
 104               issue is observed.
 105
 106         unevaluatedProperties: false
 107
 108 oneOf:
 109   - required:
 110       - ports
 111   - required:
 112       - ethernet-ports
 113
 114 required:
 115   - compatible
 116   - reg
 117
 118 unevaluatedProperties: false
 119
 120 examples:
 121   - |
 122     #include <dt-bindings/gpio/gpio.h>
 123     #include <dt-bindings/leds/common.h>
 124
 125     mdio {
 126         #address-cells = <1>;
 127         #size-cells = <0>;
 128
 129         external_phy_port1: ethernet-phy@0 {
 130             reg = <0>;
 131         };
 132
 133         external_phy_port2: ethernet-phy@1 {
 134             reg = <1>;
 135         };
 136
 137         external_phy_port3: ethernet-phy@2 {
 138             reg = <2>;
 139         };
 140
 141         external_phy_port4: ethernet-phy@3 {
 142             reg = <3>;
 143         };
 144
 145         external_phy_port5: ethernet-phy@4 {
 146             reg = <4>;
 147         };
 148
 149         switch@10 {
 150             compatible = "qca,qca8337";
 151             reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 152             reg = <0x10>;
 153
 154             ports {
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157
 158                 port@0 {
 159                     reg = <0>;
 160                     ethernet = <&gmac1>;
 161                     phy-mode = "rgmii";
 162
 163                     fixed-link {
 164                         speed = <1000>;
 165                         full-duplex;
 166                     };
 167                 };
 168
 169                 port@1 {
 170                     reg = <1>;
 171                     label = "lan1";
 172                     phy-handle = <&external_phy_port1>;
 173                 };
 174
 175                 port@2 {
 176                     reg = <2>;
 177                     label = "lan2";
 178                     phy-handle = <&external_phy_port2>;
 179                 };
 180
 181                 port@3 {
 182                     reg = <3>;
 183                     label = "lan3";
 184                     phy-handle = <&external_phy_port3>;
 185                 };
 186
 187                 port@4 {
 188                     reg = <4>;
 189                     label = "lan4";
 190                     phy-handle = <&external_phy_port4>;
 191                 };
 192
 193                 port@5 {
 194                     reg = <5>;
 195                     label = "wan";
 196                     phy-handle = <&external_phy_port5>;
 197                 };
 198             };
 199         };
 200     };
 201   - |
 202     #include <dt-bindings/gpio/gpio.h>
 203
 204     mdio {
 205         #address-cells = <1>;
 206         #size-cells = <0>;
 207
 208         switch@10 {
 209             compatible = "qca,qca8337";
 210             reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 211             reg = <0x10>;
 212
 213             ports {
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216
 217                 port@0 {
 218                     reg = <0>;
 219                     ethernet = <&gmac1>;
 220                     phy-mode = "rgmii";
 221
 222                     fixed-link {
 223                         speed = <1000>;
 224                         full-duplex;
 225                     };
 226                 };
 227
 228                 port@1 {
 229                     reg = <1>;
 230                     label = "lan1";
 231                     phy-mode = "internal";
 232                     phy-handle = <&internal_phy_port1>;
 233
 234                     leds {
 235                         #address-cells = <1>;
 236                         #size-cells = <0>;
 237
 238                         led@0 {
 239                             reg = <0>;
 240                             color = <LED_COLOR_ID_WHITE>;
 241                             function = LED_FUNCTION_LAN;
 242                             default-state = "keep";
 243                         };
 244
 245                         led@1 {
 246                             reg = <1>;
 247                             color = <LED_COLOR_ID_AMBER>;
 248                             function = LED_FUNCTION_LAN;
 249                             default-state = "keep";
 250                         };
 251                     };
 252                 };
 253
 254                 port@2 {
 255                     reg = <2>;
 256                     label = "lan2";
 257                     phy-mode = "internal";
 258                     phy-handle = <&internal_phy_port2>;
 259                 };
 260
 261                 port@3 {
 262                     reg = <3>;
 263                     label = "lan3";
 264                     phy-mode = "internal";
 265                     phy-handle = <&internal_phy_port3>;
 266                 };
 267
 268                 port@4 {
 269                     reg = <4>;
 270                     label = "lan4";
 271                     phy-mode = "internal";
 272                     phy-handle = <&internal_phy_port4>;
 273                 };
 274
 275                 port@5 {
 276                     reg = <5>;
 277                     label = "wan";
 278                     phy-mode = "internal";
 279                     phy-handle = <&internal_phy_port5>;
 280                 };
 281
 282                 port@6 {
 283                     reg = <0>;
 284                     ethernet = <&gmac1>;
 285                     phy-mode = "sgmii";
 286
 287                     qca,sgmii-rxclk-falling-edge;
 288
 289                     fixed-link {
 290                         speed = <1000>;
 291                         full-duplex;
 292                     };
 293                 };
 294             };
 295
 296             mdio {
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299
 300                 internal_phy_port1: ethernet-phy@0 {
 301                     reg = <0>;
 302                 };
 303
 304                 internal_phy_port2: ethernet-phy@1 {
 305                     reg = <1>;
 306                 };
 307
 308                 internal_phy_port3: ethernet-phy@2 {
 309                     reg = <2>;
 310                 };
 311
 312                 internal_phy_port4: ethernet-phy@3 {
 313                     reg = <3>;
 314                 };
 315
 316                 internal_phy_port5: ethernet-phy@4 {
 317                     reg = <4>;
 318                 };
 319             };
 320         };
 321     };