1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 $id: http://devicetree.org/schemas/net/dsa/mscc,ocelot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Ocelot Switch Family
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
17 derivatives of this architecture. These switches can be found embedded in
18 various SoCs and accessed using MMIO, or as discrete chips and accessed over
19 SPI or PCIe. The present DSA binding shall be used when the host controlling
20 them performs packet I/O primarily through an Ethernet port of the switch
21 (which is attached to an Ethernet port of the host), rather than through
22 Frame DMA or register-based I/O.
26 This is found in the NXP T1040, where it is a memory-mapped platform
29 The following PHY interface types are supported:
31 - phy-mode = "internal": on ports 8 and 9
32 - phy-mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
33 - phy-mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
34 - phy-mode = "1000base-x": on ports 0, 1, 2, 3, 4, 5, 6, 7
38 This is found in the NXP LS1028A. It is a PCI device, part of the larger
39 enetc root complex. As a result, the ethernet-switch node is a sub-node of
40 the PCIe root complex node and its "reg" property conforms to the parent
41 node bindings, describing it as PF 5 of device 0, bus 0.
43 If any external switch port is enabled, the enetc PF2 (enetc_port2) should
44 be enabled as well. This is because the internal MDIO bus (exposed through
45 EA BAR 0) used to access the MAC PCS registers truly belongs to the enetc
46 port 2 and not to Felix.
48 The following PHY interface types are supported:
50 - phy-mode = "internal": on ports 4 and 5
51 - phy-mode = "sgmii": on ports 0, 1, 2, 3
52 - phy-mode = "qsgmii": on ports 0, 1, 2, 3
53 - phy-mode = "usxgmii": on ports 0, 1, 2, 3
54 - phy-mode = "1000base-x": on ports 0, 1, 2, 3
55 - phy-mode = "2500base-x": on ports 0, 1, 2, 3
70 Used to signal availability of PTP TX timestamps, and state changes of
71 the MAC merge layer of ports that support Frame Preemption.
81 - $ref: dsa.yaml#/$defs/ethernet-ports
90 unevaluatedProperties: false
93 # Felix VSC9959 (NXP LS1028A)
95 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 pcie { /* Integrated Endpoint Root Complex */
101 ethernet-switch@0,5 {
102 compatible = "pci1957,eef0";
103 reg = <0x000500 0 0 0 0>;
104 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
107 #address-cells = <1>;
113 phy-handle = <&phy0>;
114 managed = "in-band-status";
120 phy-handle = <&phy1>;
121 managed = "in-band-status";
127 phy-handle = <&phy2>;
128 managed = "in-band-status";
134 phy-handle = <&phy3>;
135 managed = "in-band-status";
140 ethernet = <&enetc_port2>;
141 phy-mode = "internal";
152 ethernet = <&enetc_port3>;
153 phy-mode = "internal";
164 # Seville VSC9953 (NXP T1040)
167 #address-cells = <1>;
170 ethernet-switch@800000 {
171 compatible = "mscc,vsc9953-switch";
172 reg = <0x800000 0x290000>;
176 #address-cells = <1>;
182 phy-handle = <&phy0>;
183 managed = "in-band-status";
189 phy-handle = <&phy1>;
190 managed = "in-band-status";
196 phy-handle = <&phy2>;
197 managed = "in-band-status";
203 phy-handle = <&phy3>;
204 managed = "in-band-status";
210 phy-handle = <&phy4>;
211 managed = "in-band-status";
217 phy-handle = <&phy5>;
218 managed = "in-band-status";
224 phy-handle = <&phy6>;
225 managed = "in-band-status";
231 phy-handle = <&phy7>;
232 managed = "in-band-status";
237 phy-mode = "internal";
249 phy-mode = "internal";