1 Marvell Distributed Switch Architecture Device Tree Bindings
2 ------------------------------------------------------------
5 - compatible : Should be "marvell,dsa"
6 - #address-cells : Must be 2, first cell is the address on the MDIO bus
7 and second cell is the address in the switch tree.
8 Second cell is used only when cascading/chaining.
9 - #size-cells : Must be 0
10 - dsa,ethernet : Should be a phandle to a valid Ethernet device node
11 - dsa,mii-bus : Should be a phandle to a valid MDIO bus device node
14 - interrupts : property with a value describing the switch
15 interrupt number (not supported by the driver)
17 A DSA node can contain multiple switch chips which are therefore child nodes of
18 the parent DSA node. The maximum number of allowed child nodes is 4
20 Each of these switch child nodes should have the following required properties:
22 - reg : Contains two fields. The first one describes the
23 address on the MII bus. The second is the switch
24 number that must be unique in cascaded configurations
25 - #address-cells : Must be 1
26 - #size-cells : Must be 0
28 A switch child node has the following optional property:
30 - eeprom-length : Set to the length of an EEPROM connected to the
31 switch. Must be set if the switch can not detect
32 the presence and/or size of a connected EEPROM,
35 A switch may have multiple "port" children nodes
37 Each port children node must have the following mandatory properties:
38 - reg : Describes the port address in the switch
39 - label : Describes the label associated with this port, special
40 labels are "cpu" to indicate a CPU port and "dsa" to
41 indicate an uplink/downlink port.
43 Note that a port labelled "dsa" will imply checking for the uplink phandle
47 - link : Should be a list of phandles to another switch's DSA port.
48 This property is only used when switches are being
49 chained/cascaded together. This port is used as outgoing port
50 towards the phandle port, which can be more than one hop away.
52 - phy-handle : Phandle to a PHY on an external MDIO bus, not the
53 switch internal one. See
54 Documentation/devicetree/bindings/net/ethernet.txt
57 - phy-mode : String representing the connection to the designated
58 PHY node specified by the 'phy-handle' property. See
59 Documentation/devicetree/bindings/net/ethernet.txt
62 - mii-bus : Should be a phandle to a valid MDIO bus device node.
63 This mii-bus will be used in preference to the
64 global dsa,mii-bus defined above, for this switch.
67 - fixed-link : Fixed-link subnode describing a link to a non-MDIO
69 Documentation/devicetree/bindings/net/fixed-link.txt
75 compatible = "marvell,dsa";
80 dsa,ethernet = <ðernet0>;
81 dsa,mii-bus = <&mii_bus0>;
86 reg = <16 0>; /* MDIO address 16, switch 0 in tree */
104 switch0port6: port@6 {
107 link = <&switch1port0
113 #address-cells = <1>;
115 reg = <17 1>; /* MDIO address 17, switch 1 in tree */
116 mii-bus = <&mii_bus1>;
118 switch1port0: port@0 {
121 link = <&switch0port6>;
123 switch1port1: port@1 {
126 link = <&switch2port1>;
131 #address-cells = <1>;
133 reg = <18 2>; /* MDIO address 18, switch 2 in tree */
134 mii-bus = <&mii_bus1>;
136 switch2port0: port@0 {
139 link = <&switch1port1