1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Xilinx Axi CAN/Zynq CANPS controller
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
38 $ref: "/schemas/types.yaml#/definitions/uint32"
39 description: CAN Tx fifo depth (Zynq, Axi CAN).
42 $ref: "/schemas/types.yaml#/definitions/uint32"
43 description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
46 $ref: "/schemas/types.yaml#/definitions/uint32"
47 description: CAN Tx mailbox buffer count (CAN FD)
56 unevaluatedProperties: false
59 - $ref: can-controller.yaml#
114 #include <dt-bindings/interrupt-controller/arm-gic.h>
117 compatible = "xlnx,zynq-can-1.0";
118 reg = <0xe0008000 0x1000>;
119 clocks = <&clkc 19>, <&clkc 36>;
120 clock-names = "can_clk", "pclk";
121 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
122 interrupt-parent = <&intc>;
123 tx-fifo-depth = <0x40>;
124 rx-fifo-depth = <0x40>;
129 compatible = "xlnx,axi-can-1.00.a";
130 reg = <0x40000000 0x10000>;
131 clocks = <&clkc 0>, <&clkc 1>;
132 clock-names = "can_clk", "s_axi_aclk";
133 interrupt-parent = <&intc>;
134 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
135 tx-fifo-depth = <0x40>;
136 rx-fifo-depth = <0x40>;
141 compatible = "xlnx,canfd-1.0";
142 reg = <0x40000000 0x2000>;
143 clocks = <&clkc 0>, <&clkc 1>;
144 clock-names = "can_clk", "s_axi_aclk";
145 interrupt-parent = <&intc>;
146 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
147 tx-mailbox-count = <0x20>;
148 rx-fifo-depth = <0x20>;
153 compatible = "xlnx,canfd-2.0";
154 reg = <0xff060000 0x6000>;
155 clocks = <&clkc 0>, <&clkc 1>;
156 clock-names = "can_clk", "s_axi_aclk";
157 interrupt-parent = <&intc>;
158 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
159 tx-mailbox-count = <0x20>;
160 rx-fifo-depth = <0x40>;