1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/can/xilinx,can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Xilinx Axi CAN/Zynq CANPS controller
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
38 $ref: /schemas/types.yaml#/definitions/uint32
39 description: CAN Tx fifo depth (Zynq, Axi CAN).
42 $ref: /schemas/types.yaml#/definitions/uint32
43 description: CAN Rx fifo depth (Zynq, Axi CAN, CAN FD in sequential Rx mode)
46 $ref: /schemas/types.yaml#/definitions/uint32
47 description: CAN Tx mailbox buffer count (CAN FD)
59 unevaluatedProperties: false
62 - $ref: can-controller.yaml#
117 #include <dt-bindings/interrupt-controller/arm-gic.h>
120 compatible = "xlnx,zynq-can-1.0";
121 reg = <0xe0008000 0x1000>;
122 clocks = <&clkc 19>, <&clkc 36>;
123 clock-names = "can_clk", "pclk";
124 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-parent = <&intc>;
126 tx-fifo-depth = <0x40>;
127 rx-fifo-depth = <0x40>;
132 compatible = "xlnx,axi-can-1.00.a";
133 reg = <0x40000000 0x10000>;
134 clocks = <&clkc 0>, <&clkc 1>;
135 clock-names = "can_clk", "s_axi_aclk";
136 interrupt-parent = <&intc>;
137 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
138 tx-fifo-depth = <0x40>;
139 rx-fifo-depth = <0x40>;
144 compatible = "xlnx,canfd-1.0";
145 reg = <0x40000000 0x2000>;
146 clocks = <&clkc 0>, <&clkc 1>;
147 clock-names = "can_clk", "s_axi_aclk";
148 interrupt-parent = <&intc>;
149 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
150 tx-mailbox-count = <0x20>;
151 rx-fifo-depth = <0x20>;
156 compatible = "xlnx,canfd-2.0";
157 reg = <0xff060000 0x6000>;
158 clocks = <&clkc 0>, <&clkc 1>;
159 clock-names = "can_clk", "s_axi_aclk";
160 interrupt-parent = <&intc>;
161 interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>;
162 tx-mailbox-count = <0x20>;
163 rx-fifo-depth = <0x40>;