1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics bxCAN controller
9 description: STMicroelectronics BxCAN controller for CAN bus
12 - Dario Binacchi <dario.binacchi@amarulasolutions.com>
15 - $ref: can-controller.yaml#
24 Primary mode of the bxCAN peripheral is only relevant if the chip has
25 two CAN peripherals in dual CAN configuration. In that case they share
26 some of the required logic.
27 Not to be used if the peripheral is in single CAN configuration.
28 To avoid misunderstandings, it should be noted that ST documentation
29 uses the terms master instead of primary.
34 Secondary mode of the bxCAN peripheral is only relevant if the chip
35 has two CAN peripherals in dual CAN configuration. In that case they
36 share some of the required logic.
37 Not to be used if the peripheral is in single CAN configuration.
38 To avoid misunderstandings, it should be noted that ST documentation
39 uses the terms slave instead of secondary.
47 - description: transmit interrupt
48 - description: FIFO 0 receive interrupt
49 - description: FIFO 1 receive interrupt
50 - description: status change error interrupt
66 $ref: /schemas/types.yaml#/definitions/phandle-array
68 The phandle to the gcan node which allows to access the 512-bytes
69 SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
70 secondary) in dual CAN peripheral configuration.
80 additionalProperties: false
84 #include <dt-bindings/clock/stm32fx-clock.h>
85 #include <dt-bindings/mfd/stm32f4-rcc.h>
88 compatible = "st,stm32f4-bxcan";
89 reg = <0x40006400 0x200>;
90 interrupts = <19>, <20>, <21>, <22>;
91 interrupt-names = "tx", "rx0", "rx1", "sce";
92 resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
93 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;