1 Renesas R-Car CAN FD controller Device Tree Bindings
2 ----------------------------------------------------
5 - compatible: Must contain one or more of the following:
6 - "renesas,rcar-gen3-canfd" for R-Car Gen3 compatible controller.
7 - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
8 - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3) compatible controller.
10 When compatible with the generic version, nodes must list the
11 SoC-specific version corresponding to the platform first, followed by the
12 family-specific and/or generic versions.
14 - reg: physical base address and size of the R-Car CAN FD register map.
15 - interrupts: interrupt specifiers for the Channel & Global interrupts
16 - clocks: phandles and clock specifiers for 3 clock inputs.
17 - clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
18 - pinctrl-0: pin control group to be used for this controller.
19 - pinctrl-names: must be "default".
22 The controller supports two channels and each is represented as a child node.
23 The name of the child nodes are "channel0" and "channel1" respectively. Each
24 child node supports the "status" property only, which is used to
25 enable/disable the respective channel.
27 Required properties for "renesas,r8a7795-canfd" and "renesas,r8a7796-canfd"
29 In R8A7795 and R8A7796 SoCs, canfd clock is a div6 clock and can be used by both
30 CAN and CAN FD controller at the same time. It needs to be scaled to maximum
31 frequency if any of these controllers use it. This is done using the below
34 - assigned-clocks: phandle of canfd clock.
35 - assigned-clock-rates: maximum frequency of this clock.
38 The controller can operate in either CAN FD only mode (default) or
39 Classical CAN only mode. The mode is global to both the channels. In order to
40 enable the later, define the following optional property.
41 - renesas,no-can-fd: puts the controller in Classical CAN only mode.
46 SoC common .dtsi file:
49 compatible = "renesas,r8a7795-canfd",
50 "renesas,rcar-gen3-canfd";
51 reg = <0 0xe66c0000 0 0x8000>;
52 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&cpg CPG_MOD 914>,
55 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
57 clock-names = "fck", "canfd", "can_clk";
58 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
59 assigned-clock-rates = <40000000>;
60 power-domains = <&cpg>;
72 Board specific .dts file:
74 E.g. below enables Channel 1 alone in the board in Classical CAN only mode.
77 pinctrl-0 = <&canfd1_pins>;
78 pinctrl-names = "default";
87 E.g. below enables Channel 0 alone in the board using External clock
91 pinctrl-0 = <&canfd0_pins &can_clk_pins>;
92 pinctrl-names = "default";