1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019 BayLibre, SAS
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson DWMAC Ethernet controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
24 - amlogic,meson-axg-dwmac
25 - amlogic,meson-g12a-dwmac
30 - $ref: snps,dwmac.yaml#
36 - amlogic,meson8b-dwmac
37 - amlogic,meson8m2-dwmac
38 - amlogic,meson-gxbb-dwmac
39 - amlogic,meson-axg-dwmac
40 - amlogic,meson-g12a-dwmac
47 - description: GMAC main clock
48 - description: First parent clock of the internal mux
49 - description: Second parent clock of the internal mux
50 - description: The clock which drives the timing adjustment logic
58 - const: timing-adjustment
61 $ref: /schemas/types.yaml#/definitions/uint32
63 The internal RGMII TX clock delay (provided by this driver) in
64 nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
65 When phy-mode is set to "rgmii" then the TX delay should be
66 explicitly configured. When not configured a fallback of 2ns is
67 used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid"
68 the TX clock delay is already provided by the PHY. In that case
69 this property should be set to 0ns (which disables the TX clock
70 delay in the MAC to prevent the clock from going off because both
71 PHY and MAC are adding a delay).
72 Any configuration is ignored when the phy-mode is set to "rmii".
81 The internal RGMII RX clock delay in nanoseconds. Deprecated, use
82 rx-internal-delay-ps instead.
92 - amlogic,meson8b-dwmac
93 - amlogic,meson8m2-dwmac
94 - amlogic,meson-gxbb-dwmac
95 - amlogic,meson-axg-dwmac
108 - amlogic,meson-g12a-dwmac
111 rx-internal-delay-ps:
132 additionalItems: true
136 - amlogic,meson6-dwmac
137 - amlogic,meson8b-dwmac
138 - amlogic,meson8m2-dwmac
139 - amlogic,meson-gxbb-dwmac
140 - amlogic,meson-axg-dwmac
141 - amlogic,meson-g12a-dwmac
150 The first register range should be the one of the DWMAC controller
152 The second range is is for the Amlogic specific configuration
153 (for example the PRG_ETHERNET register range on Meson8b and newer)
164 unevaluatedProperties: false
168 ethmac: ethernet@c9410000 {
169 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
170 reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
172 interrupt-names = "macirq";
173 clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
174 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";