1 * AMD 10GbE driver (amd-xgbe)
4 - compatible: Should be "amd,xgbe-seattle-v1a"
5 - reg: Address and length of the register sets for the device
8 - SerDes Rx/Tx registers
9 - SerDes integration registers (1/2)
10 - SerDes integration registers (2/2)
11 - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
12 listed is required and is the general device interrupt. If the optional
13 amd,per-channel-interrupt property is specified, then one additional
14 interrupt for each DMA channel supported by the device should be specified.
15 The last interrupt listed should be the PCS auto-negotiation interrupt.
17 - DMA clock for the amd-xgbe device (used for calculating the
18 correct Rx interrupt watchdog timer value on a DMA channel
20 - PTP clock for the amd-xgbe device
21 - clock-names: Should be the names of the clocks
22 - "dma_clk" for the DMA clock
23 - "ptp_clk" for the PTP clock
24 - phy-mode: See ethernet.txt file in the same directory
27 - mac-address: mac address to be assigned to the device. Can be overridden
29 - dma-coherent: Present if dma operations are coherent
30 - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
31 a unique interrupt for each DMA channel - this requires an additional
32 interrupt be configured for each DMA channel
33 - amd,speed-set: Speed capabilities of the device
34 0 - 1GbE and 10GbE (default)
37 The following optional properties are represented by an array with each
38 value corresponding to a particular speed. The first array value represents
39 the setting for the 1GbE speed, the second value for the 2.5GbE speed and
40 the third value for the 10GbE speed. All three values are required if the
42 - amd,serdes-blwc: Baseline wandering correction enablement
45 - amd,serdes-cdr-rate: CDR rate speed selection
46 - amd,serdes-pq-skew: PQ (data sampling) skew
47 - amd,serdes-tx-amp: TX amplitude boost
48 - amd,serdes-dfe-tap-config: DFE taps available to run
49 - amd,serdes-dfe-tap-enable: DFE taps to enable
53 compatible = "amd,xgbe-seattle-v1a";
54 reg = <0 0xe0700000 0 0x80000>,
55 <0 0xe0780000 0 0x80000>,
56 <0 0xe1240800 0 0x00400>,
57 <0 0xe1250000 0 0x00060>,
58 <0 0xe1250080 0 0x00004>;
59 interrupt-parent = <&gic>;
60 interrupts = <0 325 4>,
61 <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
63 amd,per-channel-interrupt;
64 clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;
65 clock-names = "dma_clk", "ptp_clk";
67 mac-address = [ 02 a1 a2 a3 a4 a5 ];
69 amd,serdes-blwc = <1>, <1>, <0>;
70 amd,serdes-cdr-rate = <2>, <2>, <7>;
71 amd,serdes-pq-skew = <10>, <10>, <30>;
72 amd,serdes-tx-amp = <15>, <15>, <10>;
73 amd,serdes-dfe-tap-config = <3>, <3>, <1>;
74 amd,serdes-dfe-tap-enable = <0>, <0>, <127>;