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[releases.git] / Documentation / devicetree / bindings / net / allwinner,sun8i-a83t-emac.yaml
1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Allwinner A83t EMAC
8
9 maintainers:
10   - Chen-Yu Tsai <wens@csie.org>
11   - Maxime Ripard <mripard@kernel.org>
12
13 properties:
14   compatible:
15     oneOf:
16       - const: allwinner,sun8i-a83t-emac
17       - const: allwinner,sun8i-h3-emac
18       - const: allwinner,sun8i-r40-gmac
19       - const: allwinner,sun8i-v3s-emac
20       - const: allwinner,sun50i-a64-emac
21       - items:
22           - enum:
23               - allwinner,sun20i-d1-emac
24               - allwinner,sun50i-h6-emac
25               - allwinner,sun50i-h616-emac0
26           - const: allwinner,sun50i-a64-emac
27
28   reg:
29     maxItems: 1
30
31   interrupts:
32     maxItems: 1
33
34   interrupt-names:
35     const: macirq
36
37   clocks:
38     maxItems: 1
39
40   clock-names:
41     const: stmmaceth
42
43   syscon:
44     $ref: /schemas/types.yaml#/definitions/phandle
45     description:
46       Phandle to the device containing the EMAC or GMAC clock
47       register
48
49 required:
50   - compatible
51   - reg
52   - interrupts
53   - interrupt-names
54   - clocks
55   - clock-names
56   - resets
57   - reset-names
58   - phy-handle
59   - phy-mode
60   - syscon
61
62 allOf:
63   - $ref: "snps,dwmac.yaml#"
64   - if:
65       properties:
66         compatible:
67           contains:
68             enum:
69               - allwinner,sun8i-a83t-emac
70               - allwinner,sun8i-h3-emac
71               - allwinner,sun8i-v3s-emac
72               - allwinner,sun50i-a64-emac
73
74     then:
75       properties:
76         allwinner,tx-delay-ps:
77           default: 0
78           minimum: 0
79           maximum: 700
80           multipleOf: 100
81           description:
82             External RGMII PHY TX clock delay chain value in ps.
83
84         allwinner,rx-delay-ps:
85           default: 0
86           minimum: 0
87           maximum: 3100
88           multipleOf: 100
89           description:
90             External RGMII PHY TX clock delay chain value in ps.
91
92   - if:
93       properties:
94         compatible:
95           contains:
96             enum:
97               - allwinner,sun8i-r40-gmac
98
99     then:
100       properties:
101         allwinner,rx-delay-ps:
102           default: 0
103           minimum: 0
104           maximum: 700
105           multipleOf: 100
106           description:
107             External RGMII PHY TX clock delay chain value in ps.
108
109   - if:
110       properties:
111         compatible:
112           contains:
113             enum:
114               - allwinner,sun8i-h3-emac
115               - allwinner,sun8i-v3s-emac
116
117     then:
118       properties:
119         allwinner,leds-active-low:
120           $ref: /schemas/types.yaml#/definitions/flag
121           description:
122             EPHY LEDs are active low.
123
124         mdio-mux:
125           type: object
126           unevaluatedProperties: false
127
128           properties:
129             compatible:
130               const: allwinner,sun8i-h3-mdio-mux
131
132             mdio-parent-bus:
133               $ref: /schemas/types.yaml#/definitions/phandle
134               description:
135                 Phandle to EMAC MDIO.
136
137             "#address-cells":
138               const: 1
139
140             "#size-cells":
141               const: 0
142
143             mdio@1:
144               $ref: mdio.yaml#
145               unevaluatedProperties: false
146               description: Internal MDIO Bus
147
148               properties:
149                 compatible:
150                   const: allwinner,sun8i-h3-mdio-internal
151
152                 reg:
153                   const: 1
154
155               patternProperties:
156                 "^ethernet-phy@[0-9a-f]$":
157                   type: object
158                   description:
159                     Integrated PHY node
160
161                   properties:
162                     clocks:
163                       maxItems: 1
164
165                     resets:
166                       maxItems: 1
167
168                   required:
169                     - clocks
170                     - resets
171
172
173             mdio@2:
174               $ref: mdio.yaml#
175               unevaluatedProperties: false
176               description: External MDIO Bus (H3 only)
177
178               properties:
179                 reg:
180                   const: 2
181
182           required:
183             - compatible
184             - mdio-parent-bus
185             - mdio@1
186
187 unevaluatedProperties: false
188
189 examples:
190   - |
191     ethernet@1c0b000 {
192         compatible = "allwinner,sun8i-h3-emac";
193         syscon = <&syscon>;
194         reg = <0x01c0b000 0x104>;
195         interrupts = <0 82 1>;
196         interrupt-names = "macirq";
197         resets = <&ccu 12>;
198         reset-names = "stmmaceth";
199         clocks = <&ccu 27>;
200         clock-names = "stmmaceth";
201
202         phy-handle = <&int_mii_phy>;
203         phy-mode = "mii";
204         allwinner,leds-active-low;
205
206         mdio1: mdio {
207             #address-cells = <1>;
208             #size-cells = <0>;
209             compatible = "snps,dwmac-mdio";
210         };
211
212         mdio-mux {
213             compatible = "allwinner,sun8i-h3-mdio-mux";
214             #address-cells = <1>;
215             #size-cells = <0>;
216
217             mdio-parent-bus = <&mdio1>;
218
219             int_mii_phy: mdio@1 {
220                 compatible = "allwinner,sun8i-h3-mdio-internal";
221                 reg = <1>;
222                 #address-cells = <1>;
223                 #size-cells = <0>;
224
225                 ethernet-phy@1 {
226                     reg = <1>;
227                     clocks = <&ccu 67>;
228                     resets = <&ccu 39>;
229                     phy-is-integrated;
230                 };
231             };
232
233             mdio@2 {
234                 reg = <2>;
235                 #address-cells = <1>;
236                 #size-cells = <0>;
237             };
238         };
239     };
240
241   - |
242     ethernet@1c0b000 {
243         compatible = "allwinner,sun8i-h3-emac";
244         syscon = <&syscon>;
245         reg = <0x01c0b000 0x104>;
246         interrupts = <0 82 1>;
247         interrupt-names = "macirq";
248         resets = <&ccu 12>;
249         reset-names = "stmmaceth";
250         clocks = <&ccu 27>;
251         clock-names = "stmmaceth";
252
253         phy-handle = <&ext_rgmii_phy>;
254         phy-mode = "rgmii";
255         allwinner,leds-active-low;
256
257         mdio2: mdio {
258             #address-cells = <1>;
259             #size-cells = <0>;
260             compatible = "snps,dwmac-mdio";
261         };
262
263         mdio-mux {
264             compatible = "allwinner,sun8i-h3-mdio-mux";
265             #address-cells = <1>;
266             #size-cells = <0>;
267             mdio-parent-bus = <&mdio2>;
268
269             mdio@1 {
270                 compatible = "allwinner,sun8i-h3-mdio-internal";
271                 reg = <1>;
272                 #address-cells = <1>;
273                 #size-cells = <0>;
274
275                 ethernet-phy@1 {
276                     reg = <1>;
277                     clocks = <&ccu 67>;
278                     resets = <&ccu 39>;
279                 };
280             };
281
282             mdio@2 {
283                 reg = <2>;
284                 #address-cells = <1>;
285                 #size-cells = <0>;
286
287                 ext_rgmii_phy: ethernet-phy@1 {
288                     reg = <1>;
289                 };
290             };
291         };
292     };
293
294   - |
295     ethernet@1c0b000 {
296         compatible = "allwinner,sun8i-a83t-emac";
297         syscon = <&syscon>;
298         reg = <0x01c0b000 0x104>;
299         interrupts = <0 82 1>;
300         interrupt-names = "macirq";
301         resets = <&ccu 13>;
302         reset-names = "stmmaceth";
303         clocks = <&ccu 27>;
304         clock-names = "stmmaceth";
305         phy-handle = <&ext_rgmii_phy1>;
306         phy-mode = "rgmii";
307
308         mdio {
309             compatible = "snps,dwmac-mdio";
310             #address-cells = <1>;
311             #size-cells = <0>;
312
313             ext_rgmii_phy1: ethernet-phy@1 {
314                 reg = <1>;
315             };
316         };
317     };
318
319 ...