1 # SPDX-License-Identifier: GPL-2.0+
4 $id: http://devicetree.org/schemas/net/adi,adin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADIN1200/ADIN1300 PHY
10 - Alexandru Tachici <alexandru.tachici@analog.com>
13 Bindings for Analog Devices Industrial Ethernet PHYs
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
23 enum: [ 1600, 1800, 2000, 2200, 2400 ]
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
30 enum: [ 1600, 1800, 2000, 2200, 2400 ]
35 When operating in RMII mode, this option configures the FIFO depth.
36 enum: [ 4, 8, 12, 16, 20, 24 ]
41 Select clock output on GP_CLK pin. Two clocks are available:
42 A 25MHz reference and a free-running 125MHz.
43 The phy can alternatively automatically switch between the reference and
44 the 125MHz clocks based on its internal state.
45 $ref: /schemas/types.yaml#/definitions/string
49 - adaptive-free-running
51 adi,phy-output-reference-clock:
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
55 unevaluatedProperties: false
63 phy-mode = "rgmii-id";
68 adi,rx-internal-delay-ps = <1800>;
69 adi,tx-internal-delay-ps = <2200>;
82 adi,fifo-depth-bits = <16>;