1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NAND controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
26 - description: Core Clock
27 - description: Always ON Clock
34 "#address-cells": true
52 - $ref: "nand-controller.yaml#"
58 const: qcom,ipq806x-nand
63 - description: rxtx DMA channel
70 $ref: /schemas/types.yaml#/definitions/uint32
72 Must contain the ADM command type CRCI block instance number
73 specified for the NAND controller on the given platform
76 $ref: /schemas/types.yaml#/definitions/uint32
78 Must contain the ADM data type CRCI block instance number
79 specified for the NAND controller on the given platform
95 - description: tx DMA channel
96 - description: rx DMA channel
97 - description: cmd DMA channel
111 unevaluatedProperties: false
115 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
116 nand-controller@1ac00000 {
117 compatible = "qcom,ipq806x-nand";
118 reg = <0x1ac00000 0x800>;
120 clocks = <&gcc EBI2_CLK>,
122 clock-names = "core", "aon";
126 qcom,cmd-crci = <15>;
127 qcom,data-crci = <3>;
129 #address-cells = <1>;
135 nand-ecc-strength = <4>;
136 nand-bus-width = <8>;
139 compatible = "fixed-partitions";
140 #address-cells = <1>;
150 reg = <0x58a0000 0x4000000>;
156 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
157 nand-controller@79b0000 {
158 compatible = "qcom,ipq4019-nand";
159 reg = <0x79b0000 0x1000>;
161 clocks = <&gcc GCC_QPIC_CLK>,
162 <&gcc GCC_QPIC_AHB_CLK>;
163 clock-names = "core", "aon";
168 dma-names = "tx", "rx", "cmd";
170 #address-cells = <1>;
175 nand-ecc-strength = <4>;
176 nand-bus-width = <8>;
179 compatible = "fixed-partitions";
180 #address-cells = <1>;
190 reg = <0x58a0000 0x4000000>;