1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers supporting only one chip.
19 The ECC strength and ECC step size properties define the user
20 desires in terms of correction capability of a controller. Together,
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
25 not all implementations must support all possible
26 combinations. However, implementations are encouraged to further
27 specify the value(s) they support.
31 pattern: "^nand-controller(@.*)?"
43 Array of chip-select available to the controller. The first
44 entries are a 1:1 mapping of the available chip-select on the
45 NAND controller (even if they are not used). As many additional
46 chip-select as needed may follow and should be phandles of GPIO
47 lines. 'reg' entries of the NAND chip subnodes become indexes of
48 this array when this property is present.
55 $ref: "nand-chip.yaml#"
60 Contains the chip-select IDs.
64 Location of the ECC bytes. This location is unknown by default
65 but can be explicitly set to "oob", if all ECC bytes are
66 known to be stored in the OOB area, or "interleaved" if ECC
67 bytes will be interleaved with regular data in the main area.
68 $ref: /schemas/types.yaml#/definitions/string
69 enum: [ oob, interleaved ]
73 Bus width to the NAND chip
74 $ref: /schemas/types.yaml#/definitions/uint32
80 With this property, the OS will search the device for a Bad
81 Block Table (BBT). If not found, it will create one, reserve
82 a few blocks at the end of the device to store it and update
83 it as the device ages. Otherwise, the out-of-band area of a
84 few pages of all the blocks will be scanned at boot time to
85 find Bad Block Markers (BBM). These markers will help to
86 build a volatile BBT in RAM.
87 $ref: /schemas/types.yaml#/definitions/flag
91 Whether or not the ECC strength should be maximized. The
92 maximum ECC strength is both controller and chip
93 dependent. The ECC engine has to select the ECC config
94 providing the best strength and taking the OOB area size
95 constraint into account. This is particularly useful when
96 only the in-band area is used by the upper layers, and you
97 want to make your NAND as reliable as possible.
98 $ref: /schemas/types.yaml#/definitions/flag
102 Whether or not the NAND chip is a boot medium. Drivers might
103 use this information to select ECC algorithms supported by
104 the boot ROM or similar restrictions.
105 $ref: /schemas/types.yaml#/definitions/flag
109 Contains the native Ready/Busy IDs.
110 $ref: /schemas/types.yaml#/definitions/uint32-array
114 Contains one or more GPIO descriptor (the numper of descriptor
115 depends on the number of R/B pins exposed by the flash) for the
116 Ready/Busy pins. Active state refers to the NAND ready state and
117 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
121 Contains one GPIO descriptor for the Write Protect pin.
122 Active state refers to the NAND Write Protect state and should be
123 set to GPIOD_ACTIVE_LOW unless the signal is inverted.
133 additionalProperties: true
138 #address-cells = <1>;
140 cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
142 /* controller specific properties */
145 reg = <0>; /* Native CS */
146 /* NAND chip specific properties */
150 reg = <1>; /* GPIO CS */