1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers supporting only one chip.
19 The ECC strength and ECC step size properties define the user
20 desires in terms of correction capability of a controller. Together,
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
25 not all implementations must support all possible
26 combinations. However, implementations are encouraged to further
27 specify the value(s) they support.
31 pattern: "^nand-controller(@.*)?"
47 Contains the chip-select IDs.
51 Desired ECC engine, either hardware (most of the time
52 embedded in the NAND controller) or software correction
53 (Linux will handle the calculations). soft_bch is deprecated
54 and should be replaced by soft and nand-ecc-algo.
55 $ref: /schemas/types.yaml#/definitions/string
56 enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
60 - $ref: /schemas/types.yaml#/definitions/phandle
62 A phandle on the hardware ECC engine if any. There are
63 basically three possibilities:
64 1/ The ECC engine is part of the NAND controller, in this
65 case the phandle should reference the parent node.
66 2/ The ECC engine is part of the NAND part (on-die), in this
67 case the phandle should reference the node itself.
68 3/ The ECC engine is external, in this case the phandle should
69 reference the specific ECC engine node.
71 nand-use-soft-ecc-engine:
73 description: Use a software ECC engine.
77 description: Do not use any ECC correction.
81 - $ref: /schemas/types.yaml#/definitions/string
82 - enum: [ oob, interleaved ]
84 Location of the ECC bytes. This location is unknown by default
85 but can be explicitly set to "oob", if all ECC bytes are
86 known to be stored in the OOB area, or "interleaved" if ECC
87 bytes will be interleaved with regular data in the main area.
91 Desired ECC algorithm.
92 $ref: /schemas/types.yaml#/definitions/string
93 enum: [hamming, bch, rs]
97 Bus width to the NAND chip
98 $ref: /schemas/types.yaml#/definitions/uint32
103 $ref: /schemas/types.yaml#/definitions/flag
105 With this property, the OS will search the device for a Bad
106 Block Table (BBT). If not found, it will create one, reserve
107 a few blocks at the end of the device to store it and update
108 it as the device ages. Otherwise, the out-of-band area of a
109 few pages of all the blocks will be scanned at boot time to
110 find Bad Block Markers (BBM). These markers will help to
111 build a volatile BBT in RAM.
115 Maximum number of bits that can be corrected per ECC step.
116 $ref: /schemas/types.yaml#/definitions/uint32
121 Number of data bytes covered by a single ECC step.
122 $ref: /schemas/types.yaml#/definitions/uint32
126 $ref: /schemas/types.yaml#/definitions/flag
128 Whether or not the ECC strength should be maximized. The
129 maximum ECC strength is both controller and chip
130 dependent. The ECC engine has to select the ECC config
131 providing the best strength and taking the OOB area size
132 constraint into account. This is particularly useful when
133 only the in-band area is used by the upper layers, and you
134 want to make your NAND as reliable as possible.
137 $ref: /schemas/types.yaml#/definitions/flag
139 Whether or not the NAND chip is a boot medium. Drivers might
140 use this information to select ECC algorithms supported by
141 the boot ROM or similar restrictions.
144 $ref: /schemas/types.yaml#/definitions/uint32-array
146 Contains the native Ready/Busy IDs.
150 Contains one or more GPIO descriptor (the numper of descriptor
151 depends on the number of R/B pins exposed by the flash) for the
152 Ready/Busy pins. Active state refers to the NAND ready state and
153 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
162 additionalProperties: true
167 #address-cells = <1>;
170 /* controller specific properties */
174 nand-ecc-mode = "soft";
175 nand-ecc-algo = "bch";
177 /* NAND chip specific properties */