1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
13 Flash chips (Memory Technology Devices) are often used for solid state
14 file systems on embedded devices.
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
31 - cortina,gemini-flash
33 - ge,imp3a-firmware-mirror
34 - ge,imp3a-paged-flash
35 - gef,ppc9a-firmware-mirror
36 - gef,ppc9a-paged-flash
37 - gef,sbc310-firmware-mirror
38 - gef,sbc310-paged-flash
39 - gef,sbc610-firmware-mirror
40 - gef,sbc610-paged-flash
46 - intel,PC28F640P30T85
50 - xlnx,xps-mch-emc-2.00.a
56 - cypress,cy7c1019dv33-10zsxi
67 It's possible to (optionally) define multiple "reg" tuples so that
68 non-identical chips can be described in one node.
73 description: Width (in bytes) of the bank. Equal to the device width times
74 the number of interleaved chips.
75 $ref: /schemas/types.yaml#/definitions/uint32
80 Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'.
81 $ref: /schemas/types.yaml#/definitions/uint32
84 no-unaligned-direct-access:
87 Disables the default direct mapping of the flash.
89 On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems
90 with JFFS2 usage, as the local bus (LPB) doesn't support unaligned
91 accesses as implemented in the JFFS2 code via memcpy(). By defining
92 "no-unaligned-direct-access", the flash will not be exposed directly to
93 the MTD users (e.g. JFFS2) any more.
97 Allows specifying the mtd name for retro capability with physmap-flash
98 drivers as boot loader pass the mtd partition via the old device name
100 $ref: /schemas/types.yaml#/definitions/string
102 use-advanced-sector-protection:
105 Enables support for the advanced sector protection (Spansion: PPB -
106 Persistent Protection Bits) locking.
109 description: The chip's physical erase block size in bytes.
110 $ref: /schemas/types.yaml#/definitions/uint32
114 List of GPIO descriptors that will be used to address the MSBs address
115 lines. The order goes from LSB to MSB.
136 const: cortina,gemini-flash
140 $ref: /schemas/types.yaml#/definitions/phandle
142 Phandle to the syscon controller
146 # FIXME: A parent bus may define timing properties
147 additionalProperties: true
153 compatible = "cfi-flash";
154 reg = <0xff000000 0x01000000>;
158 #address-cells = <1>;
160 ranges = <0 0xff000000 0x01000000>;
168 reg = <0xf80000 0x80000>;
174 /* An example with multiple "reg" tuples */
177 compatible = "intel,PC28F640P30T85", "cfi-flash";
178 reg = <0x00000000 0x02000000>,
179 <0x02000000 0x02000000>;
182 #address-cells = <1>;
184 ranges = <0 0 0x04000000>;
187 label = "test-part1";
188 reg = <0 0x04000000>;
193 /* An example using SRAM */
195 #address-cells = <2>;
199 compatible = "mtd-ram";
200 reg = <2 0 0x00200000>;
206 /* An example using addr-gpios */
207 #include <dt-bindings/gpio/gpio.h>
210 compatible = "cfi-flash";
211 reg = <0x20000000 0x02000000>;
213 addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
215 #address-cells = <1>;
217 ranges = <0 0x00000000 0x02000000>,
218 <1 0x02000000 0x02000000>;
221 label = "test-part1";
222 reg = <0 0x04000000>;