1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
10 - Rob Herring <robh@kernel.org>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
20 - pattern: "^((((micron|spansion|st),)?\
21 (m25p(40|80|16|32|64|128)|\
22 n25q(32b|064|128a11|128a13|256a|512a|164k)))|\
23 atmel,at25df(321a|641|081a)|\
24 everspin,mr25h(10|40|128|256)|\
25 (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\
26 (mxicy|macronix),mx25u(4033|4035)|\
27 (spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\
28 (sst|microchip),sst25vf(016b|032b|040b)|\
30 (sst,)?sst25wf(040b|080)|\
32 (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
33 - const: jedec,spi-nor
43 - const: jedec,spi-nor
44 - const: jedec,spi-nor
46 Must also include "jedec,spi-nor" for any SPI NOR flash that can be
47 identified by the JEDEC READ ID opcode (0x9F).
56 Use the "fast read" opcode to read data from the chip instead of the usual
57 "read" opcode. This opcode is not supported by all chips and support for
58 it can not be detected at runtime. Refer to your chips' datasheet to check
59 if this is supported by your chip.
64 Some flash devices utilize stateful addressing modes (e.g., for 32-bit
65 addressing) which need to be managed carefully by a system. Because these
66 sorts of flash don't have a standardized software reset command, and
67 because some systems don't toggle the flash RESET# pin upon system reset
68 (if the pin even exists at all), there are systems which cannot reboot
69 properly if the flash is left in the "wrong" state. This boolean flag can
70 be used on such systems, to denote the absence of a reliable reset
76 '#address-cells': true
80 # Note: use 'partitions' node for new users
91 spi-cpol: [ spi-cpha ]
92 spi-cpha: [ spi-cpol ]
94 unevaluatedProperties: false
103 compatible = "spansion,m25p80", "jedec,spi-nor";
105 spi-max-frequency = <40000000>;