1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware Mobile Storage Host Controller
10 - Ulf Hansson <ulf.hansson@linaro.org>
12 # Everything else is described in the common file
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
30 Handle to "biu" and "ciu" clocks for the
31 bus interface unit clock and the card interface unit clock.
39 $ref: /schemas/types.yaml#/definitions/phandle-array
42 - description: phandle to the sysmgr node
43 - description: register offset that controls the SDMMC clock phase
44 - description: register shift for the smplsel(drive in) setting
46 This property is optional. Contains the phandle to System Manager block
47 that contains the SDMMC clock-phase control register. The first value is
48 the pointer to the sysmgr, the 2nd value is the register offset for the
49 SDMMC clock phase register, and the 3rd value is the bit shift for the
50 smplsel(drive in) setting.
53 - $ref: synopsys-dw-mshc-common.yaml#
59 const: altr,socfpga-dw-mshc
62 altr,sysmgr-syscon: true
65 altr,sysmgr-syscon: false
74 unevaluatedProperties: false
79 compatible = "snps,dw-mshc";
80 reg = <0x12200000 0x1000>;
81 interrupts = <0 75 0>;
82 clocks = <&clock 351>, <&clock 132>;
83 clock-names = "biu", "ciu";
87 reset-names = "reset";
88 vmmc-supply = <&buck8>;
95 card-detect-delay = <200>;
96 max-frequency = <200000000>;
97 clock-frequency = <400000000>;
100 fifo-watermark-aligned;