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[releases.git] / Documentation / devicetree / bindings / mmc / snps,dwcmshc-sdhci.yaml
1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Synopsys Designware Mobile Storage Host Controller Binding
8
9 maintainers:
10   - Ulf Hansson <ulf.hansson@linaro.org>
11   - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
12
13 allOf:
14   - $ref: mmc-controller.yaml#
15
16 properties:
17   compatible:
18     enum:
19       - rockchip,rk3568-dwcmshc
20       - rockchip,rk3588-dwcmshc
21       - snps,dwcmshc-sdhci
22
23   reg:
24     maxItems: 1
25
26   interrupts:
27     maxItems: 1
28
29   clocks:
30     minItems: 1
31     items:
32       - description: core clock
33       - description: bus clock for optional
34       - description: axi clock for rockchip specified
35       - description: block clock for rockchip specified
36       - description: timer clock for rockchip specified
37
38
39   clock-names:
40     minItems: 1
41     items:
42       - const: core
43       - const: bus
44       - const: axi
45       - const: block
46       - const: timer
47
48   rockchip,txclk-tapnum:
49     description: Specify the number of delay for tx sampling.
50     $ref: /schemas/types.yaml#/definitions/uint8
51
52
53 required:
54   - compatible
55   - reg
56   - interrupts
57   - clocks
58   - clock-names
59
60 unevaluatedProperties: false
61
62 examples:
63   - |
64     mmc@fe310000 {
65       compatible = "rockchip,rk3568-dwcmshc";
66       reg = <0xfe310000 0x10000>;
67       interrupts = <0 25 0x4>;
68       clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>;
69       clock-names = "core", "bus", "axi", "block", "timer";
70       bus-width = <8>;
71       #address-cells = <1>;
72       #size-cells = <0>;
73     };
74   - |
75     mmc@aa0000 {
76       compatible = "snps,dwcmshc-sdhci";
77       reg = <0xaa000 0x1000>;
78       interrupts = <0 25 0x4>;
79       clocks = <&cru 17>, <&cru 18>;
80       clock-names = "core", "bus";
81       bus-width = <8>;
82       #address-cells = <1>;
83       #size-cells = <0>;
84     };
85
86 ...