1 * Qualcomm SDHCI controller (sdhci-msm)
3 This file documents differences between the core properties in mmc.txt
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain:
8 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
9 "qcom,sdhci-msm-v5" for sdcc versions >= 5.0
10 For SDCC version 5.0.0, MCI registers are removed from SDCC
11 interface and some registers are moved to HC. New compatible
12 string is added to support this change - "qcom,sdhci-msm-v5".
13 - reg: Base address and length of the register in the following order:
14 - Host controller register map (required)
15 - SD Core register map (required)
16 - interrupts: Should contain an interrupt-specifiers for the interrupts:
17 - Host controller interrupt (required)
18 - pinctrl-names: Should contain only one value - "default".
19 - pinctrl-0: Should specify pin control groups used for this controller.
20 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
21 - clock-names: Should contain the following:
22 "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
23 "core" - SDC MMC clock (MCLK) (required)
24 "bus" - SDCC bus voter clock (optional)
25 "xo" - TCXO clock (optional)
26 "cal" - reference clock for RCLK delay calibration (optional)
27 "sleep" - sleep clock for RCLK delay calibration (optional)
31 sdhc_1: sdhci@f9824900 {
32 compatible = "qcom,sdhci-msm-v4";
33 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
34 interrupts = <0 123 0>;
38 vmmc-supply = <&pm8941_l20>;
39 vqmmc-supply = <&pm8941_s3>;
41 pinctrl-names = "default";
42 pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
44 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
45 clock-names = "core", "iface";
48 sdhc_2: sdhci@f98a4900 {
49 compatible = "qcom,sdhci-msm-v4";
50 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
51 interrupts = <0 125 0>;
53 cd-gpios = <&msmgpio 62 0x1>;
55 vmmc-supply = <&pm8941_l21>;
56 vqmmc-supply = <&pm8941_l13>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
61 clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
62 clock-names = "core", "iface";