1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
9 Storage Host Controller
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-dw-mshc
19 - samsung,exynos4412-dw-mshc
20 - samsung,exynos5250-dw-mshc
21 - samsung,exynos5420-dw-mshc
22 - samsung,exynos5420-dw-mshc-smu
23 - samsung,exynos7-dw-mshc
24 - samsung,exynos7-dw-mshc-smu
25 - axis,artpec8-dw-mshc
36 Handle to "biu" and "ciu" clocks for the
37 bus interface unit clock and the card interface unit clock.
44 samsung,dw-mshc-ciu-div:
45 $ref: /schemas/types.yaml#/definitions/uint32
49 The divider value for the card interface unit (ciu) clock.
51 samsung,dw-mshc-ddr-timing:
52 $ref: /schemas/types.yaml#/definitions/uint32-array
54 - description: CIU clock phase shift value for tx mode
57 - description: CIU clock phase shift value for rx mode
61 The value of CUI clock phase shift value in transmit mode and CIU clock
62 phase shift value in receive mode for double data rate mode operation.
63 See also samsung,dw-mshc-hs400-timing property.
65 samsung,dw-mshc-hs400-timing:
66 $ref: /schemas/types.yaml#/definitions/uint32-array
68 - description: CIU clock phase shift value for tx mode
71 - description: CIU clock phase shift value for rx mode
75 The value of CIU TX and RX clock phase shift value for HS400 mode
77 Valid values for SDR and DDR CIU clock timing::
78 - valid value for tx phase shift and rx phase shift is 0 to 7.
79 - when CIU clock divider value is set to 3, all possible 8 phase shift
81 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
82 phase shift clocks should be 0.
83 If missing, values from samsung,dw-mshc-ddr-timing property are used.
85 samsung,dw-mshc-sdr-timing:
86 $ref: /schemas/types.yaml#/definitions/uint32-array
88 - description: CIU clock phase shift value for tx mode
91 - description: CIU clock phase shift value for rx mode
95 The value of CIU clock phase shift value in transmit mode and CIU clock
96 phase shift value in receive mode for single data rate mode operation.
97 See also samsung,dw-mshc-hs400-timing property.
99 samsung,read-strobe-delay:
100 $ref: /schemas/types.yaml#/definitions/uint32
102 RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
103 line in Read path). If missing, default from hardware is used.
111 - samsung,dw-mshc-ddr-timing
112 - samsung,dw-mshc-sdr-timing
115 - $ref: "synopsys-dw-mshc-common.yaml#"
121 - samsung,exynos5250-dw-mshc
122 - samsung,exynos5420-dw-mshc
123 - samsung,exynos7-dw-mshc
124 - samsung,exynos7-dw-mshc-smu
125 - axis,artpec8-dw-mshc
128 - samsung,dw-mshc-ciu-div
130 unevaluatedProperties: false
134 #include <dt-bindings/clock/exynos5420.h>
135 #include <dt-bindings/interrupt-controller/arm-gic.h>
138 compatible = "samsung,exynos5420-dw-mshc";
139 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
140 #address-cells = <1>;
142 reg = <0x12220000 0x1000>;
143 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
144 clock-names = "biu", "ciu";
146 card-detect-delay = <200>;
147 samsung,dw-mshc-ciu-div = <3>;
148 samsung,dw-mshc-sdr-timing = <0 4>;
149 samsung,dw-mshc-ddr-timing = <0 2>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
154 max-frequency = <200000000>;
155 vmmc-supply = <&ldo19_reg>;
156 vqmmc-supply = <&ldo13_reg>;