1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip designware mobile storage host controller device tree bindings
10 Rockchip uses the Synopsys designware mobile storage host controller
11 to interface a SoC with storage medium such as eMMC or SD/MMC cards.
12 This file documents the combined properties for the core Synopsys dw mshc
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
14 file and the Rockchip specific extensions.
17 - $ref: "synopsys-dw-mshc-common.yaml#"
20 - Heiko Stuebner <heiko@sntech.de>
22 # Everything else is described in the common file
26 # for Rockchip RK2928 and before RK3288
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
32 - rockchip,px30-dw-mshc
33 - rockchip,rk1808-dw-mshc
34 - rockchip,rk3036-dw-mshc
35 - rockchip,rk3228-dw-mshc
36 - rockchip,rk3308-dw-mshc
37 - rockchip,rk3328-dw-mshc
38 - rockchip,rk3368-dw-mshc
39 - rockchip,rk3399-dw-mshc
40 - rockchip,rk3568-dw-mshc
41 - rockchip,rv1108-dw-mshc
42 - const: rockchip,rk3288-dw-mshc
54 Handle to "biu" and "ciu" clocks for the bus interface unit clock and
55 the card interface unit clock. If "ciu-drive" and "ciu-sample" are
56 specified in clock-names, it should also contain
57 handles to these clocks.
67 Apart from the clock-names "biu" and "ciu" two more clocks
68 "ciu-drive" and "ciu-sample" are supported. They are used
69 to control the clock phases, "ciu-sample" is required for tuning
72 rockchip,default-sample-phase:
73 $ref: /schemas/types.yaml#/definitions/uint32
78 The default phase to set "ciu-sample" at probing,
79 low speeds or in case where all phases work at tuning time.
80 If not specified 0 deg will be used.
82 rockchip,desired-num-phases:
83 $ref: /schemas/types.yaml#/definitions/uint32
88 The desired number of times that the host execute tuning when needed.
89 If not specified, the host will do tuning for 360 times,
90 namely tuning for each degree.
99 unevaluatedProperties: false
103 #include <dt-bindings/clock/rk3288-cru.h>
104 #include <dt-bindings/interrupt-controller/arm-gic.h>
105 #include <dt-bindings/interrupt-controller/irq.h>
106 sdmmc: mmc@ff0c0000 {
107 compatible = "rockchip,rk3288-dw-mshc";
108 reg = <0xff0c0000 0x4000>;
109 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
111 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
112 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
113 resets = <&cru SRST_MMC0>;
114 reset-names = "reset";
115 fifo-depth = <0x100>;
116 max-frequency = <150000000>;