1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas SDHI SD/MMC controller
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
16 - const: renesas,sdhi-sh73a0 # R-Mobile APE6
18 - const: renesas,sdhi-r7s72100 # RZ/A1H
20 - const: renesas,sdhi-r7s9210 # SH-Mobile AG5
22 - const: renesas,sdhi-r8a73a4 # R-Mobile APE6
24 - const: renesas,sdhi-r8a7740 # R-Mobile A1
27 - renesas,sdhi-r8a7778 # R-Car M1
28 - renesas,sdhi-r8a7779 # R-Car H1
29 - const: renesas,rcar-gen1-sdhi # R-Car Gen1
32 - renesas,sdhi-r8a7742 # RZ/G1H
33 - renesas,sdhi-r8a7743 # RZ/G1M
34 - renesas,sdhi-r8a7744 # RZ/G1N
35 - renesas,sdhi-r8a7745 # RZ/G1E
36 - renesas,sdhi-r8a77470 # RZ/G1C
37 - renesas,sdhi-r8a7790 # R-Car H2
38 - renesas,sdhi-r8a7791 # R-Car M2-W
39 - renesas,sdhi-r8a7792 # R-Car V2H
40 - renesas,sdhi-r8a7793 # R-Car M2-N
41 - renesas,sdhi-r8a7794 # R-Car E2
42 - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1
44 - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
47 - renesas,sdhi-r8a774a1 # RZ/G2M
48 - renesas,sdhi-r8a774b1 # RZ/G2N
49 - renesas,sdhi-r8a774c0 # RZ/G2E
50 - renesas,sdhi-r8a774e1 # RZ/G2H
51 - renesas,sdhi-r8a7795 # R-Car H3
52 - renesas,sdhi-r8a7796 # R-Car M3-W
53 - renesas,sdhi-r8a77961 # R-Car M3-W+
54 - renesas,sdhi-r8a77965 # R-Car M3-N
55 - renesas,sdhi-r8a77970 # R-Car V3M
56 - renesas,sdhi-r8a77980 # R-Car V3H
57 - renesas,sdhi-r8a77990 # R-Car E3
58 - renesas,sdhi-r8a77995 # R-Car D3
59 - renesas,sdhi-r8a779a0 # R-Car V3U
60 - renesas,sdhi-r9a07g043 # RZ/G2UL
61 - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
62 - renesas,sdhi-r9a07g054 # RZ/V2L
63 - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
106 - $ref: "mmc-controller.yaml"
113 - renesas,sdhi-r9a07g043
114 - renesas,sdhi-r9a07g044
115 - renesas,sdhi-r9a07g054
120 - description: IMCLK, SDHI channel main clock1.
121 - description: CLK_HS, SDHI channel High speed clock which operates
122 4 times that of SDHI channel main clock1.
123 - description: IMCLK2, SDHI channel main clock2. When this clock is
124 turned off, external SD card detection cannot be
126 - description: ACLK, SDHI channel bus clock.
142 - renesas,rcar-gen2-sdhi
143 - renesas,rcar-gen3-sdhi
171 const: renesas,sdhi-mmc-r8a77470
190 - renesas,sdhi-r7s72100
191 - renesas,sdhi-r7s9210
196 The internal card detection logic that exists in these controllers is
197 sectioned off to be run by a separate second clock source to allow
198 the main core clock to be turned off to save power.
207 unevaluatedProperties: false
211 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
212 #include <dt-bindings/interrupt-controller/arm-gic.h>
213 #include <dt-bindings/power/r8a7790-sysc.h>
215 sdhi0: mmc@ee100000 {
216 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
217 reg = <0xee100000 0x328>;
218 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&cpg CPG_MOD 314>;
220 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
221 dma-names = "tx", "rx", "tx", "rx";
222 max-frequency = <195000000>;
223 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
227 sdhi1: mmc@ee120000 {
228 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
229 reg = <0xee120000 0x328>;
230 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&cpg CPG_MOD 313>;
232 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
233 dma-names = "tx", "rx", "tx", "rx";
234 max-frequency = <195000000>;
235 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
239 sdhi2: mmc@ee140000 {
240 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
241 reg = <0xee140000 0x100>;
242 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cpg CPG_MOD 312>;
244 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
245 dma-names = "tx", "rx", "tx", "rx";
246 max-frequency = <97500000>;
247 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
251 sdhi3: mmc@ee160000 {
252 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
253 reg = <0xee160000 0x100>;
254 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&cpg CPG_MOD 311>;
256 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
257 dma-names = "tx", "rx", "tx", "rx";
258 max-frequency = <97500000>;
259 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;