1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MTK MSDC Storage Host Controller Binding
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
14 - $ref: mmc-controller.yaml#
30 - const: mediatek,mt7623-mmc
31 - const: mediatek,mt2701-mmc
33 - const: mediatek,mt8192-mmc
34 - const: mediatek,mt8183-mmc
36 - const: mediatek,mt8195-mmc
37 - const: mediatek,mt8183-mmc
41 Should contain phandle for the clock feeding the MMC controller.
44 - description: source clock (required).
45 - description: HCLK which used for host (required).
46 - description: independent source clock gate (required for MT2712).
47 - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
48 - description: msdc subsys clock gate (required for MT8192).
49 - description: peripheral bus clock gate (required for MT8192).
50 - description: AXI bus clock gate (required for MT8192).
51 - description: AHB bus clock gate (required for MT8192).
72 should contain default/high speed pin ctrl.
77 should contain uhs mode pin ctrl.
82 PLL of the source clock.
85 assigned-clock-parents:
87 parent of source clock, used for HS400 mode to get 400Mhz source clock.
91 $ref: /schemas/types.yaml#/definitions/uint32
93 HS400 DS delay setting.
97 mediatek,hs200-cmd-int-delay:
98 $ref: /schemas/types.yaml#/definitions/uint32
100 HS200 command internal delay setting.
101 This field has total 32 stages.
102 The value is an integer from 0 to 31.
106 mediatek,hs400-cmd-int-delay:
107 $ref: /schemas/types.yaml#/definitions/uint32
109 HS400 command internal delay setting.
110 This field has total 32 stages.
111 The value is an integer from 0 to 31.
115 mediatek,hs400-cmd-resp-sel-rising:
116 $ref: /schemas/types.yaml#/definitions/flag
118 HS400 command response sample selection.
119 If present, HS400 command responses are sampled on rising edges.
120 If not present, HS400 command responses are sampled on falling edges.
123 $ref: /schemas/types.yaml#/definitions/uint32
125 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
126 data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
127 if not present, default value is 0.
128 applied to compatible "mediatek,mt2701-mmc".
150 unevaluatedProperties: false
154 #include <dt-bindings/interrupt-controller/irq.h>
155 #include <dt-bindings/interrupt-controller/arm-gic.h>
156 #include <dt-bindings/clock/mt8173-clk.h>
158 compatible = "mediatek,mt8173-mmc";
159 reg = <0x11230000 0x1000>;
160 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
161 vmmc-supply = <&mt6397_vemc_3v3_reg>;
162 vqmmc-supply = <&mt6397_vio18_reg>;
163 clocks = <&pericfg CLK_PERI_MSDC30_0>,
164 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
165 clock-names = "source", "hclk";
166 pinctrl-names = "default", "state_uhs";
167 pinctrl-0 = <&mmc0_pins_default>;
168 pinctrl-1 = <&mmc0_pins_uhs>;
169 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
170 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
171 hs400-ds-delay = <0x14015>;
172 mediatek,hs200-cmd-int-delay = <26>;
173 mediatek,hs400-cmd-int-delay = <14>;
174 mediatek,hs400-cmd-resp-sel-rising;