1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC Controller Generic Binding
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 These properties are common to multiple MMC host controllers. Any host
14 that requires the respective functionality should implement them using
17 It is possible to assign a fixed index mmcN to an MMC host controller
18 (and the corresponding mmcblkN devices) by defining an alias in the
19 /aliases device tree node.
23 pattern: "^mmc(@.*)?$"
28 The cell is the slot ID if a function subnode is used.
34 # If none of these properties are supplied, the host native card
35 # detect will be used. Only one of them should be provided.
38 $ref: /schemas/types.yaml#/definitions/flag
40 There is no card detection available; polling must be used.
45 The card detection will be done using the GPIO provided.
48 $ref: /schemas/types.yaml#/definitions/flag
50 Non-removable slot (like eMMC); assume always present.
52 # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
53 # controllers line polarity properties, we have to fix the meaning
54 # of the "normal" and "inverted" line levels. We choose to follow
55 # the SDHCI standard, which specifies both those lines as "active
56 # low." Therefore, using the "cd-inverted" property means, that the
57 # CD line is active high, i.e. it is high, when a card is
58 # inserted. Similar logic applies to the "wp-inverted" property.
60 # CD and WP lines can be implemented on the hardware in one of two
61 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
62 # as dedicated pins. Polarity of dedicated pins can be specified,
63 # using *-inverted properties. GPIO polarity can also be specified
64 # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
65 # latter case. We choose to use the XOR logic for GPIO CD and WP
66 # lines. This means, the two properties are "superimposed," for
67 # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
68 # respective *-inverted property property results in a
69 # double-inversion and actually means the "normal" line polarity is
72 $ref: /schemas/types.yaml#/definitions/flag
74 The Write Protect line polarity is inverted.
77 $ref: /schemas/types.yaml#/definitions/flag
79 The CD line polarity is inverted.
86 $ref: /schemas/types.yaml#/definitions/uint32
92 Maximum operating frequency of the bus.
93 $ref: /schemas/types.yaml#/definitions/uint32
98 $ref: /schemas/types.yaml#/definitions/flag
100 When set, no physical write-protect line is present. This
101 property should only be specified when the controller has a
102 dedicated write-protect detection logic. If a GPIO is always used
103 for the write-protect detection logic, it is sufficient to not
104 specify the wp-gpios property in the absence of a write-protect
105 line. Not used in combination with eMMC or SDIO.
110 GPIO to use for the write-protect detection.
112 cd-debounce-delay-ms:
114 Set delay time before detecting card after card insert
118 $ref: /schemas/types.yaml#/definitions/flag
120 When specified, denotes that 1.8V card voltage is not supported
121 on this system, even if the controller claims it.
124 $ref: /schemas/types.yaml#/definitions/flag
126 SD high-speed timing is supported.
129 $ref: /schemas/types.yaml#/definitions/flag
131 MMC high-speed timing is supported.
134 $ref: /schemas/types.yaml#/definitions/flag
136 SD UHS SDR12 speed is supported.
139 $ref: /schemas/types.yaml#/definitions/flag
141 SD UHS SDR25 speed is supported.
144 $ref: /schemas/types.yaml#/definitions/flag
146 SD UHS SDR50 speed is supported.
149 $ref: /schemas/types.yaml#/definitions/flag
151 SD UHS SDR104 speed is supported.
154 $ref: /schemas/types.yaml#/definitions/flag
156 SD UHS DDR50 speed is supported.
159 $ref: /schemas/types.yaml#/definitions/flag
161 Powering off the card is safe.
164 $ref: /schemas/types.yaml#/definitions/flag
166 eMMC hardware reset is supported
169 $ref: /schemas/types.yaml#/definitions/flag
171 enable SDIO IRQ signalling on this interface
174 $ref: /schemas/types.yaml#/definitions/flag
176 Full power cycle of the card is supported.
178 full-pwr-cycle-in-suspend:
179 $ref: /schemas/types.yaml#/definitions/flag
181 Full power cycle of the card in suspend is supported.
184 $ref: /schemas/types.yaml#/definitions/flag
186 eMMC high-speed DDR mode (1.2V I/O) is supported.
189 $ref: /schemas/types.yaml#/definitions/flag
191 eMMC high-speed DDR mode (1.8V I/O) is supported.
194 $ref: /schemas/types.yaml#/definitions/flag
196 eMMC high-speed DDR mode (3.3V I/O) is supported.
199 $ref: /schemas/types.yaml#/definitions/flag
201 eMMC HS200 mode (1.2V I/O) is supported.
204 $ref: /schemas/types.yaml#/definitions/flag
206 eMMC HS200 mode (1.8V I/O) is supported.
209 $ref: /schemas/types.yaml#/definitions/flag
211 eMMC HS400 mode (1.2V I/O) is supported.
214 $ref: /schemas/types.yaml#/definitions/flag
216 eMMC HS400 mode (1.8V I/O) is supported.
218 mmc-hs400-enhanced-strobe:
219 $ref: /schemas/types.yaml#/definitions/flag
221 eMMC HS400 enhanced strobe mode is supported
224 $ref: /schemas/types.yaml#/definitions/flag
226 All eMMC HS400 modes are not supported.
230 Value the card Driver Stage Register (DSR) should be programmed
232 $ref: /schemas/types.yaml#/definitions/uint32
237 $ref: /schemas/types.yaml#/definitions/flag
239 Controller is limited to send SDIO commands during
243 $ref: /schemas/types.yaml#/definitions/flag
245 Controller is limited to send SD commands during initialization.
248 $ref: /schemas/types.yaml#/definitions/flag
250 Controller is limited to send MMC commands during
253 fixed-emmc-driver-type:
255 For non-removable eMMC, enforce this driver type. The value is
256 the driver type as specified in the eMMC specification (table
257 206 in spec version 5.1)
258 $ref: /schemas/types.yaml#/definitions/uint32
262 post-power-on-delay-ms:
264 It was invented for MMC pwrseq-simple which could be referred to
265 mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay
266 waiting for I/O signalling and card power supply to be stable,
267 regardless of whether pwrseq-simple is used. Default to 10ms if
272 $ref: /schemas/types.yaml#/definitions/flag
274 The presence of this property indicates that the corresponding
275 MMC host controller supports HW command queue feature.
278 $ref: /schemas/types.yaml#/definitions/flag
280 The presence of this property indicates that the MMC
281 controller\'s command queue engine (CQE) does not support direct
284 keep-power-in-suspend:
285 $ref: /schemas/types.yaml#/definitions/flag
287 SDIO only. Preserves card power during a suspend/resume cycle.
289 # Deprecated: enable-sdio-wakeup
291 $ref: /schemas/types.yaml#/definitions/flag
293 SDIO only. Enables wake up of host system on SDIO IRQ assertion.
297 Supply for the card power
301 Supply for the bus IO line power, such as a level shifter.
302 If the level shifter is controlled by a GPIO line, this shall
303 be modeled as a "regulator-fixed" with a GPIO line for
304 switching the level shifter on/off.
307 $ref: /schemas/types.yaml#/definitions/phandle
309 System-on-Chip designs may specify a specific MMC power
310 sequence. To successfully detect an (e)MMC/SD/SDIO card, that
311 power sequence must be maintained while initializing the card.
317 On embedded systems the cards connected to a host may need
318 additional properties. These can be specified in subnodes to the
319 host controller node. The subnodes are identified by the
320 standard \'reg\' property. Which information exactly can be
321 specified depends on the bindings for the SDIO function driver
322 for the subnode, as specified by the compatible string.
327 Name of SDIO function following generic names recommended
335 Must contain the SDIO function number of the function this
336 subnode describes. A value of 0 denotes the memory SD
337 function, values from 1 to 7 denote the SDIO functions.
342 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
343 $ref: /schemas/types.yaml#/definitions/uint32-array
351 Set the clock (phase) delays which are to be configured in the
352 controller while switching to particular speed mode. These values
353 are in pair of degrees.
356 cd-debounce-delay-ms: [ cd-gpios ]
357 fixed-emmc-driver-type: [ non-removable ]
359 additionalProperties: true
364 #address-cells = <1>;
366 reg = <0x1c12000 0x200>;
367 pinctrl-names = "default";
368 pinctrl-0 = <&mmc3_pins_a>;
369 vmmc-supply = <®_vmmc3>;
372 mmc-pwrseq = <&sdhci0_pwrseq>;
376 compatible = "brcm,bcm4329-fmac";
377 interrupt-parent = <&pio>;
379 interrupt-names = "host-wake";