1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Xenon SDHCI Controller
10 This file documents differences between the core MMC properties described by
11 mmc-controller.yaml and the properties used by the Xenon implementation.
13 Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
14 Each SDHC is independent and owns independent resources, such as register
17 Each SDHC should have an independent device tree node.
20 - Ulf Hansson <ulf.hansson@linaro.org>
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
30 - const: marvell,armada-ap807-sdhci
31 - const: marvell,armada-ap806-sdhci
34 - const: marvell,armada-3700-sdhci
35 - const: marvell,sdhci-xenon
41 For "marvell,armada-3700-sdhci", two register areas. The first one
42 for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
43 Voltage Control register. Please follow the examples with compatible
44 "marvell,armada-3700-sdhci" in below.
45 Please also check property marvell,pad-type in below.
47 For other compatible strings, one register area for Xenon IP.
62 marvell,xenon-sdhc-id:
63 $ref: /schemas/types.yaml#/definitions/uint32
67 Indicate the corresponding bit index of current SDHC in SDHC System
68 Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
69 enable/disable current SDHC.
71 marvell,xenon-phy-type:
72 $ref: /schemas/types.yaml#/definitions/string
77 Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
78 marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
79 choice if this property is not provided. To select eMMC 5.0 PHY, set:
80 marvell,xenon-phy-type = "emmc 5.0 phy"
82 All those types of PHYs can support eMMC, SD and SDIO. Please note that
83 this property only presents the type of PHY. It doesn't stand for the
84 entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
85 that this Xenon SDHC only supports eMMC 5.1.
87 marvell,xenon-phy-znr:
88 $ref: /schemas/types.yaml#/definitions/uint32
94 Only available for eMMC PHY.
96 marvell,xenon-phy-zpr:
97 $ref: /schemas/types.yaml#/definitions/uint32
103 Only available for eMMC PHY.
105 marvell,xenon-phy-nr-success-tun:
106 $ref: /schemas/types.yaml#/definitions/uint32
111 Set the number of required consecutive successful sampling points
112 used to identify a valid sampling window, in tuning process.
114 marvell,xenon-phy-tun-step-divider:
115 $ref: /schemas/types.yaml#/definitions/uint32
118 Set the divider for calculating TUN_STEP.
120 marvell,xenon-phy-slow-mode:
123 If this property is selected, transfers will bypass PHY.
124 Only available when bus frequency lower than 55MHz in SDR mode.
125 Disabled by default. Please only try this property if timing issues
126 always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
127 SD Default Speed and HS mode and eMMC legacy speed mode.
129 marvell,xenon-tun-count:
130 $ref: /schemas/types.yaml#/definitions/uint32
133 Xenon SDHC SoC usually doesn't provide re-tuning counter in
134 Capabilities Register 3 Bit[11:8].
135 This property provides the re-tuning counter.
138 - $ref: mmc-controller.yaml#
143 const: marvell,armada-3700-sdhci
149 - description: Xenon IP registers
150 - description: Armada 3700 SoC PHY PAD Voltage Control register
153 $ref: /schemas/types.yaml#/definitions/string
158 Type of Armada 3700 SoC PHY PAD Voltage Controller register.
159 If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
160 and is switched to 1.8V when later in higher speed mode.
161 If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
163 Please follow the examples with compatible
164 "marvell,armada-3700-sdhci" in below.
174 - marvell,armada-cp110-sdhci
175 - marvell,armada-ap807-sdhci
176 - marvell,armada-ap806-sdhci
195 unevaluatedProperties: false
200 #include <dt-bindings/interrupt-controller/arm-gic.h>
201 #include <dt-bindings/interrupt-controller/irq.h>
204 compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
205 reg = <0xaa0000 0x1000>;
206 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&emmc_clk 0>, <&axi_clk 0>;
208 clock-names = "core", "axi";
210 marvell,xenon-phy-slow-mode;
211 marvell,xenon-tun-count = <11>;
216 /* Vmmc and Vqmmc are both fixed */
221 #include <dt-bindings/interrupt-controller/arm-gic.h>
222 #include <dt-bindings/interrupt-controller/irq.h>
225 compatible = "marvell,armada-cp110-sdhci";
226 reg = <0xab0000 0x1000>;
227 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
228 vqmmc-supply = <&sd_vqmmc_regulator>;
229 vmmc-supply = <&sd_vmmc_regulator>;
230 clocks = <&sdclk 0>, <&axi_clk 0>;
231 clock-names = "core", "axi";
233 marvell,xenon-tun-count = <9>;
237 // For eMMC with compatible "marvell,armada-3700-sdhci":
238 #include <dt-bindings/interrupt-controller/arm-gic.h>
239 #include <dt-bindings/interrupt-controller/irq.h>
242 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
243 reg = <0xaa0000 0x1000>,
245 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&emmcclk 0>;
247 clock-names = "core";
255 /* Vmmc and Vqmmc are both fixed */
257 marvell,pad-type = "fixed-1-8v";
261 // For SD/SDIO with compatible "marvell,armada-3700-sdhci":
262 #include <dt-bindings/interrupt-controller/arm-gic.h>
263 #include <dt-bindings/interrupt-controller/irq.h>
266 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
267 reg = <0xab0000 0x1000>,
269 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
270 vqmmc-supply = <&sd_regulator>;
273 clock-names = "core";
276 marvell,pad-type = "sd";