1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
13 - $ref: mmc-controller.yaml
19 - microchip,mpfs-sd4hc
20 - socionext,uniphier-sd4hc
32 # PHY DLL input delays:
33 # They are used to delay the data valid window, and align the window to
34 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
35 # and it is increased by 2.5ns in each step.
37 cdns,phy-input-delay-sd-highspeed:
38 description: Value of the delay in the input path for SD high-speed timing
39 $ref: "/schemas/types.yaml#/definitions/uint32"
43 cdns,phy-input-delay-legacy:
44 description: Value of the delay in the input path for legacy timing
45 $ref: "/schemas/types.yaml#/definitions/uint32"
49 cdns,phy-input-delay-sd-uhs-sdr12:
50 description: Value of the delay in the input path for SD UHS SDR12 timing
51 $ref: "/schemas/types.yaml#/definitions/uint32"
55 cdns,phy-input-delay-sd-uhs-sdr25:
56 description: Value of the delay in the input path for SD UHS SDR25 timing
57 $ref: "/schemas/types.yaml#/definitions/uint32"
61 cdns,phy-input-delay-sd-uhs-sdr50:
62 description: Value of the delay in the input path for SD UHS SDR50 timing
63 $ref: "/schemas/types.yaml#/definitions/uint32"
67 cdns,phy-input-delay-sd-uhs-ddr50:
68 description: Value of the delay in the input path for SD UHS DDR50 timing
69 $ref: "/schemas/types.yaml#/definitions/uint32"
73 cdns,phy-input-delay-mmc-highspeed:
74 description: Value of the delay in the input path for MMC high-speed timing
75 $ref: "/schemas/types.yaml#/definitions/uint32"
79 cdns,phy-input-delay-mmc-ddr:
80 description: Value of the delay in the input path for eMMC high-speed DDR timing
82 # PHY DLL clock delays:
83 # Each delay property represents the fraction of the clock period.
84 # The approximate delay value will be
85 # (<delay property value>/128)*sdmclk_clock_period.
86 $ref: "/schemas/types.yaml#/definitions/uint32"
90 cdns,phy-dll-delay-sdclk:
92 Value of the delay introduced on the sdclk output for all modes except
93 HS200, HS400 and HS400_ES.
94 $ref: "/schemas/types.yaml#/definitions/uint32"
98 cdns,phy-dll-delay-sdclk-hsmmc:
100 Value of the delay introduced on the sdclk output for HS200, HS400 and
101 HS400_ES speed modes.
102 $ref: "/schemas/types.yaml#/definitions/uint32"
106 cdns,phy-dll-delay-strobe:
108 Value of the delay introduced on the dat_strobe input used in
109 HS400 / HS400_ES speed modes.
110 $ref: "/schemas/types.yaml#/definitions/uint32"
120 unevaluatedProperties: false
125 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
126 reg = <0x5a000000 0x400>;
127 interrupts = <0 78 4>;
133 cdns,phy-dll-delay-sdclk = <0>;