1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
11 - Piotr Sroka <piotrs@cadence.com>
14 - $ref: mmc-controller.yaml
20 - microchip,mpfs-sd4hc
21 - socionext,uniphier-sd4hc
33 # PHY DLL input delays:
34 # They are used to delay the data valid window, and align the window to
35 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
36 # and it is increased by 2.5ns in each step.
38 cdns,phy-input-delay-sd-highspeed:
39 description: Value of the delay in the input path for SD high-speed timing
40 $ref: "/schemas/types.yaml#/definitions/uint32"
44 cdns,phy-input-delay-legacy:
45 description: Value of the delay in the input path for legacy timing
46 $ref: "/schemas/types.yaml#/definitions/uint32"
50 cdns,phy-input-delay-sd-uhs-sdr12:
51 description: Value of the delay in the input path for SD UHS SDR12 timing
52 $ref: "/schemas/types.yaml#/definitions/uint32"
56 cdns,phy-input-delay-sd-uhs-sdr25:
57 description: Value of the delay in the input path for SD UHS SDR25 timing
58 $ref: "/schemas/types.yaml#/definitions/uint32"
62 cdns,phy-input-delay-sd-uhs-sdr50:
63 description: Value of the delay in the input path for SD UHS SDR50 timing
64 $ref: "/schemas/types.yaml#/definitions/uint32"
68 cdns,phy-input-delay-sd-uhs-ddr50:
69 description: Value of the delay in the input path for SD UHS DDR50 timing
70 $ref: "/schemas/types.yaml#/definitions/uint32"
74 cdns,phy-input-delay-mmc-highspeed:
75 description: Value of the delay in the input path for MMC high-speed timing
76 $ref: "/schemas/types.yaml#/definitions/uint32"
80 cdns,phy-input-delay-mmc-ddr:
81 description: Value of the delay in the input path for eMMC high-speed DDR timing
83 # PHY DLL clock delays:
84 # Each delay property represents the fraction of the clock period.
85 # The approximate delay value will be
86 # (<delay property value>/128)*sdmclk_clock_period.
87 $ref: "/schemas/types.yaml#/definitions/uint32"
91 cdns,phy-dll-delay-sdclk:
93 Value of the delay introduced on the sdclk output for all modes except
94 HS200, HS400 and HS400_ES.
95 $ref: "/schemas/types.yaml#/definitions/uint32"
99 cdns,phy-dll-delay-sdclk-hsmmc:
101 Value of the delay introduced on the sdclk output for HS200, HS400 and
102 HS400_ES speed modes.
103 $ref: "/schemas/types.yaml#/definitions/uint32"
107 cdns,phy-dll-delay-strobe:
109 Value of the delay introduced on the dat_strobe input used in
110 HS400 / HS400_ES speed modes.
111 $ref: "/schemas/types.yaml#/definitions/uint32"
121 unevaluatedProperties: false
126 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
127 reg = <0x5a000000 0x400>;
128 interrupts = <0 78 4>;
134 cdns,phy-dll-delay-sdclk = <0>;